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2021-09-28TOSA: Decomposition of CONCATPatrik Gustavsson
-Added support for unlimited number of dimensions -Added support for Tensors with dimension size exceeding maximum limit of NPU. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I3cc7327ac759e69042a600e686160aeb18a5ec59
2021-09-21TOSA: Decompose elem op tensorsPatrik Gustavsson
Added decomposition of tensors exceeding maximum size supported by NPU. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I17a99cb72947d2f1064a631ad6975ce895c258d5
2021-09-20TOSA: Elementwise Rank > 4 and Batch > 1Patrik Gustavsson
Added support for elementwise operations: -Support for up to Rank == 6 -Support for Batch > 1 for Rank == 4 -For binary elementwise ops this includes handling of broadcasting in dimensions above H-dimension Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I73850bbfb288077a99bd2ceecbf989172016da24
2021-09-15TOSA: Support for TABLE operator (int8)Patrik Gustavsson
Added support to map TABLE operator to LUT. Limitations: -Only supported for int8 -TABLE input must be constant This also adds the support for TFLite legalisation of Tanh/Sigmoid (int8/uint8). Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I1a95f61fb02fdd42c4a690494418cc0765c8b275
2021-09-15MLBEDSW-5102 Update removal of memory only operatorsJonas Ohlsson
Memory only operators such as Reshape, Squeeze and ExpandDims are removed in the graph optimiser step. - Added semantic check that memory only operators have same quantisation parameters on ifm/ofm. - Added support for the ExpandDims operator. - Addition and cleanup of related unit tests. - Removed TOSA from the generated SUPPORTED_OPS.md documentation. Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com> Change-Id: If848d8afc58c18806e10997ed94e4dae83f30879
2021-09-15MLBEDSW-5052 Fix RELU scalingFredrik Svedberg
Fixed scaling for RELUs with different IFM/OFM scaling. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I0ac96326b3960c0fb025b885e06a259d24b2e684
2021-09-10MLBEDSW-5174: Third-party custom ops not passed through correctlyTim Hall
- Re-added the CustomOptionsSerializer to the CUSTOM op TFLite mapping Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I51b141749ba223c132190077eed9e22fac798d2d
2021-09-09TOSA: Support for standalone CLAMP/RELUPatrik Gustavsson
Added support for standalone CLAMP/RELU. Limited to: -Rank <= 4 -N = 1 if Rank = 4 Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: If1a32fb330ce6c67c09ec4b554b4a0688444d5f0
2021-09-09TOSA: Add support for PADPatrik Gustavsson
Added support for TOSA PAD operator in line with legacy support Limitations: -Rank <= 4 -N = 1 if Rank = 4 for ifms/ofm -only padding in W and H dimensions -bool_t not supported Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I511608202b4c9bf6d86285b559c517fb41741fdf
2021-09-08TOSA: Fix AVGPOOL scalingPatrik Gustavsson
-Only support for avgpool when there is no padding. For this case, global scaling can be used. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I026b83b05f02c57c79f49935f5ec501a6d28bb91
2021-09-07TOSA: Added RESHAPE, SLICE and CONCATPatrik Gustavsson
Added support for Data layout ops RESHAPE, SLICE and CONCAT. -No support for bool_t -Support limited to Rank <= 4 and N = 1 Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I487ac494b6506a2a6ba947ee758aa193194dd796
2021-09-07MLBEDSW-5160 Fix constant data move to fast storagePatrik Gustavsson
Additional check added for when constant data can be moved to fast storage. Do not move constant data for concat. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ib8b5fd1483ee9fabe48e9874a5723af9b7c5231a
2021-09-06MLBEDSW-4975 Fix semodepth assertsJacob Bohlin
This commit fixes one assert regarding rolling buffers for 3D tensors. It also addresses another issue where the incorrect weight buffering was proposed for cascaded operators. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I2501f35e5668b3085d917751cfc8002d250973d8
2021-09-03TOSA: Added support for ADD, SUB and MULPatrik Gustavsson
Added support for ADD, SUB and MUL Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I52acdc126b16e2cf4096bcf7a77023ea7d204998
2021-09-03TOSA: Added Depthwise supportPatrik Gustavsson
This is mainly to add support for depthwise conv2d with dephmultiplier = 1. (But there are no testcases suited, all I have sourced has depth_multiplier set to 2, which is not supported.) -Added support for depthwise conv2d. -Added support for removing Transpose of constant data -Added support for removing reshape Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I143e6246becfa78fd9f7510af0bf0d6b3fbbf2c7
2021-09-03MLBEDSW-5056 Output diff wav2letter (int16)Fredrik Svedberg
Fixed output diff for wav2letter int16 by correcting the scaling used for LeakyRelu. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I8be1e14c25d223dc6e42c4ec498ff4d3d9de65d7
2021-09-03TOSA: Support for AVGPOOL, MAXPOOL and CONV2DPatrik Gustavsson
Added support for -AVGPOOL and CONV2D with TFLite correspondence -MAXPOOL -additional support for replacing RESCALE ops with avgpool. No support for breaking down tensors over the size supported by NPU. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I1d2aa50ac30a26283b3e6f1fe88cba1544b7c189
2021-09-01TOSA raw data outputDiqing Zhong
- Add TOSA output generation in npz format Change-Id: I97822e3a93a8fef1a95a990f23ef2c4ca5a8f73a Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2021-08-25Handle sg input and output for Squeeze operator3.1.0.rc2Jonas Ohlsson
Update to handle the case when the Squeeze Op ifm/ofm are the subgraph ifm/ofm, to facilitate the removal of the Squeeze Op. Adding NOP to maintain the original tensors. Updated pytests for squeeze operator. Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com> Change-Id: I623cae05e696fb16ccf29dedc42fd822601e9fd9
2021-08-23Step up external API versionDwight Lidman
A commit pertaining to MLBEDSW-4738 where the functionality of find_block_configs() in the external API was reinstated had previously been merged, but was done without increasing the API version. This commit amends that mistake. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I32f559d626e0f4e93c522813b6f4e12beaa50e57
2021-08-23Reinstate recursion limit CLI optionDwight Lidman
This commit adds a CLI option for setting the recursion limit. This option was originally removed because it was considered unnecessary, but in some cases of very large (enormous) networks, a RecursionError is encountered during graph traversal. A simple solution for issues like those is to manually increase the recursion limit. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Id0dbf68edf59b151abfa91783b5f8f021c1bb40f
2021-08-23MLBEDSW-4978: Cascading of operators requiring full IFM/OFMLouis Verhaard
Bug fix in cascade builder: tensors produced with operators requiring full OFM or consumed by operators requiring full IFM could be added as intermediate buffers to a cascade. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: Id84e9e1940bf85ab4cbc42a03e65f64da16a094c
2021-08-23vela: Remove unused shared_buffer_allocation.pyTim Hall
- Deleted file as it was no longer needed Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I03df2fc98964b96f4c7eabcf98dd5baa19de78ca
2021-08-23MLBEDSW-4913 Fix inception_v1/v3 output diffJonas Ohlsson
Fix inception_v1/v3 output diffs. Removing the Squeeze operator in the graph optimisation step. The squeeze operator removes dimensions of size 1 from tensor shape. The memory layout is preserved. Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com> Change-Id: I4ceffcbb141af5ed50b0d1a9d1d67622e638c2a1
2021-08-23MLBEDSW-4976: index errors in schedulerLouis Verhaard
- Fixed index error in memory_snapshot - When removing a cascade, also references are removed Change-Id: I2b35dc52671d8ce115eb32bfdd93584391d1fc6d Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-08-19Revert "Revert "MLBEDSW-5028: SRAM target exceeded for legacy_sram_size test ↵patrik.gustavsson
option"" This reverts commit 257a31e93cb2c7a8c06a102211ebb05b3ba78cd8. Reason for revert: <INSERT REASONING HERE> Change-Id: If4f565d8c692e2b32903819561591d9e4af619fa
2021-08-19Revert "MLBEDSW-5028: SRAM target exceeded for legacy_sram_size test option"patrik.gustavsson
Relationship to other patches This reverts commit b6dd9c2e5fcf2885fb42dab567378c8aec22215c. Reason for revert: <INSERT REASONING HERE> Change-Id: I50afb5ac4e33e5b8cd4f2aac1f5b94700ab8eeb1
2021-08-19MLBEDSW-5028: SRAM target exceeded for legacy_sram_size test optionTim Hall
- Changed mem_type_size() to only return a hard limit Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ia9271c54a592965f88f52fe25a52b3efaca88500
2021-08-19MLBEDSW-4641 Bugfix Inception v3 hangJacob Bohlin
Fixed a bug that caused the constant and buffered weights to expect different encoding. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I77acee29d104bc7c8e132907e61a72b581ace0e5
2021-08-16MLBEDSW-4738 Reinstate find_block_config from v2.1Jacob Bohlin
Reinstated the v2.1.0 functionality for find_block_configs(). This is used exclusively by the external API. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I6977f13866957edb083769658cc8c57c2b3556fb
2021-08-16MLBEDSW-4803: Output diff fix for MobileNetV33.1.0.rc1Dwight Lidman
This commit moves a piece of code back into a loop but with a flag to make sure that the code is only executed once per loop rather than potentially every iteration. This solves the issue of an output diff because of LUT DMAs occurring before weight DMAs. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I3e597f0a955154af3d87febacea1b3920d53b7c2
2021-08-13MLBEDSW-4993: TFLite mapping error for Wav2LetterDwight Lidman
Previous to this commit some networks were failing due one or more options in the TFLite mapping being incorrect after the update to match TF 2.5. This commit reverts those changes. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Ia0b577ca44d76486fc3e0ea9780e0dc1d2baf65e
2021-08-11vela: Fix Ethos-U65 maximum address rangeTim Hall
- Changed Ethos-65 AXI port address width from 48 to 40-bits - Fixed the use of arena_cache_size in mem_type_size() to cover the arena as well as the cache memory area Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I826462a0cbd0c061cccbc7c83dde446778a2b1ca
2021-08-11MLBEDSW-4838 TOSA const data input changesPatrik Gustavsson
Adoptions related to changes for constant data in TOSA. Constant data not longer stored in .npy files, but within the .tosa-file. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ia1148c2f8b783b3926a1ee0b9ad0a3aeff9d22f5
2021-08-10MLBEDSW-3319: Bring-up tests regression fixDwight Lidman
A number of bring-up were failing after the update to TensorFlow 2.3. After updating to TensorFlow 2.5 the problems persisted and more failures were introduced when they were expected to be solved. However, with this small patch that changes the rounding mode for ResizeBilinear, all tests now pass. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I5f2f3859b9008187ca318d5270da7b850b170b18
2021-08-05MLBEDSW-4854: Update to TensorFlow 2.5Dwight Lidman
This commit updates the flatbuffers generated code to comply with TensorFlow 2.5, as well as stripping away some legacy code. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I01fe47ec2bde6e78fdde21ee1bc0a71f560c53ae
2021-07-28MLBEDSW-4974: create_const_tensor invalid argumentTim Hall
- Fix bug with MEAN ops calling create_const_tensor using the quant_value_dtype keyword argument. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I8cff542ae840fb110ea97c0cc86bb761d5a884d3
2021-07-27MLBEDSW-4853: Refactor supported operatorsJonas Ohlsson
Refactor supported operators by breaking out model semantics into its own class. Model semantics checked right after model read. Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com> Change-Id: If442b189efcd91dda01af60b2b3adedfacdf2fad
2021-07-26MLBEDSW-4892: Fix weight compression of asymmetrically dilated kernels.James Peet
Signed-off-by: James Peet <james.peet@arm.com> Change-Id: I5bf39aa4f1fb48bcb0423edc4cd1d01f59aac1db
2021-07-26MLBEDSW-4892: Fix crash affecting biases without quantization.James Peet
Remove quant_values attribute from Tensor class. It only needs a single values attribute, holding either quantized or unquantized values as appropriate. Change-Id: Ie96f80ac58061b6077e0f7048dc60209fdfbcafa Signed-off-by: James Peet <james.peet@arm.com>
2021-07-19MLBEDSW-4812: Deep speech performance block config updateTim Hall
Deep speech was exhibiting poor performance in its first three layers due to poor SHRAM utilisation. - Given a choice between multiple identical-cost block configs, the allocator was choosing the first one it encountered. This commit biases the choice towards blocks with a larger IFM fetch area to improve SHRAM utilisation. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I2ff18a13444b8812cb451a606ff692bf290e7d20
2021-07-09MLBEDSW-4839: Fix issues with Elementwise IFM/OFM overlapTim Hall
- Fixed typo with not using ifm.mem_type - Fixed bug with using ifm1 properties when only ifm2 is a potential match - Removed restriction on not considering SHL and SHR for overlap - Removed some dead reshape code Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Id9bcc3c2b3ee9ac7b6276187d3e2f513b4acd4b5
2021-07-09MLBEDSW-4840 Move setting of input indices to tflite readerPatrik Gustavsson
Mapping to internal input indexing has been added to tflite_reader.py and tosa_reader.py. And the other way around in tflite_writer.py. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I4d8596e747cfa7c4203884c4e785eb1977e2bcc1
2021-07-08MLBEDSW-4838 Added basic TOSA support.Patrik Gustavsson
Added basic TOSA support, enabling Vela to read and compile a .tosa file corresponding to CONV2D + Rescale + Clamp, and writing it to an optimized .tflite file. The optimized .tflite file, will in this case, hold a commandstream where the Rescale and Clamp has been fused into the CONV2D. The optimized tflite file is not output from Vela. -Added support to read .tosa file into Vela internal structure. - Added tosa_reader.py, tosa_mapper.py and helper files stored under tosa/ - Support for this limited to ~10 ops -Added reader_util.py for functions common for TOSA and TFLite -Added tosa_graph_optimiser.py -Added support to fuse Rescale into convolution -Modified handling for padding -Added support to fuse Clamp to previous op -Added graph_optimiser_util.py -Moved functions common for TOSA/TFLite graph optimization to this file. -Renamed graph_optimiser.py to tflite_graph_optmiser.py -Added separate tosa_supported_operators.py -Added supported_operator_util.py -For functions in common for TOSA/TFLite Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ic3c540504ec8c5eb4771397fdc6882050ecf33ab
2021-07-05MLBEDSW-3890 handling scratch tensorSamuel Panijel
vela: Possible issue with handling scratch tensor on non-ethosu custom op Fixing a case where a tensor input name ends with "scratch". 4 test cases passing this change: 1) non-optimized tflite - input tensor name is _split_1_scratch 2) optimized tflite - input tensor name is _split_1_scratch 3) optimized tflite - input tensor name is _split_1_scratch and custom operation name is non_ethus_u 4) non-optimized tflite - input tensor name is _split_1_scratch_fast Change-Id: Ia515805825b7f9a646607c5075b7ea3a0cf6aad8 Signed-off-by: Samuel Panijel <samuel.panijel@arm.com>
2021-06-25MLBEDSW-4819: MLCE: weight_compressor int has no attribute astypeTim Hall
- Added type checking so that the correct type conversion can be used Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ia83f46029fac7bad63844c090b87d23c2072b105
2021-06-22MLBEDSW-4807 Elementwise IFM/OFM overlapJacob Bohlin
Reinstated allowing the IFM and OFM tensor to overlap for Elementwise operations. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: Ide6db7781f3ca7a36c8ff9e3efdc7943a7bf6d7f
2021-06-17Block config optimisation for 256/512 configurationsTim Hall
- 256 and 512 configuration variants execute 1D convolutions in an optimised manner compared to their 2x2 microblock dimensions. This commit takes this into account to improve Conv1D throughput on these configurations. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I6ecdf6e4a219e356327b22f8393f50ee8817af23
2021-06-17vela: Improve block configuration and weight buffering algorithmTim Hall
- Update block config selection to take into account partial IFM fetches at edge of non-whole OFM block data. - Change to scheduler depth slicing for networks in MLBEDSW-4637 for improved buffering. This helps general performance by buffering larger depth slices. - Bug fix for opt_max_schedule always being fitted to SRAM which prevented the optimisation step running in some cases. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I97642c5adec3bb684b1daabf2b81574c27d4eef2
2021-06-16MLBEDSW-4635: yolo_v3 output diffJacob Bohlin
Fixed an issue where the scheduler would set the incorrect tensor layout. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I28abdf3f3c523d7da0cf8840316ece37dad364ab
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