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- There is a problem with large networks containing many NPU
subgraphs. The scheduling takes too long time since the snapshot
memory calculation is always doing a complete update for the
full graph.
- A complete run is needed in the end to calculate all the
time indexes correctly. However, when scheduling a NPU subgraph
it is enough to extract live ranges for the current schedule
and its operators.
Change-Id: Iccb7d6728119c1428ad0b45a2ac34e92158c15bd
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- The assert was caused due to a faulty optimization being done
in the pass packing when trying to group CPU passes. The code
did not take into account that a CPU op could have many outputs.
-The fix is to make sure that the pass the follows the CPU pass is
not dependent on any of the outputs from the CPU pass. If there is a
dependency the CPU pass cannot be moved.
Change-Id: Ia0c90bae1ed97d503a97e7bc353f834a0fa75130
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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Adding constraint for faulty reshape operators. Number of elements
for IFM and OFM must be the same.
Change-Id: I2e31e9d1e39b5aa3a0c595032a66e14374a0719e
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- The problem was that when the split slice read was moved
to the tensor consumer, in this case an elementwise operator,
this was not taken into account when the npu op for the
element wise operator was created. The npu op was created
with wrong ifm_width and ifm and ifm2 ended up with different
sizes. As a result, broadcasting is expected but that is
not True so the assert was triggered.
- The fix is to use the ifm box in order to set the correct
ifm_width for the npu operator.
Change-Id: I3291d34e7f8e7add9caf2296cca600c60e96bf7e
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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shrinking an axis
- The problem was that the end values of STRIDED_SLICE operators
were not taking the shrink_axis_mask into account
- The fix is simply to ignore the end value set on the operator
and calculate one based upon shrinking the axis
Change-Id: I2e5f2d3c9b08035dfd9b1629c775408f2356d1cf
Signed-off-by: Tim Hall <tim.hall@arm.com>
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Changed default behaviour to place int8 ops with asymmetric quantization on cpu, and added an option to force symmetric quantization
Change-Id: Ib9b717aaf61eae78833254ca3dfa745f4f253dc6
Signed-off-by: wilisa01 <william.isaksson@arm.com>
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Swapped order of ifms to add in tflite graph optimiser.
The output diff was caused by the second input tensor being placed on sram, despite there being no dma request to move it there.
Change-Id: I2e83b669ba226c7e96a0bb0d46ba811434cf7bb6
Signed-off-by: wilisa01 <william.isaksson@arm.com>
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- The problem was that networks with resource variables have
not been thought of. The major problem was the graph traversal
where these ops were not visited resulting in an empty subgraph
that resulted in the crash.
- Fixed the problem by attaching virtual tensors to the ops simulating
subgraph output. These tensors are only used to get the graph
traversal to work.
- Fixed serializing of attribute container and shared_name
- Fixed subgraph index for operator CallOnce
- All resource variable ops are pushed to the CPU
Change-Id: I815f9c81baf7a3fbb686e895980b462f58208b6e
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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Added support for Variable Tensor, including offline planning.
Change-Id: I39f33fee207f1f1a4574a0f53f7377eec8709e15
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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Since test works by creating an overflow, sets NumPy to ignore overflow for this test case
Change-Id: I74d03e8d73455295168352542dcb844283d54d33
Signed-off-by: wilisa01 <william.isaksson@arm.com>
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Some copyright years of files in the mlw_codec had not been updated
during changes in late 2022.
Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
Change-Id: Iebab154127e5868202a805aff0125154ac1d3beb
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Sets second input tensor of resize op to be constant and refactored function.
Signed-off-by: wilisa01 <william.isaksson@arm.com>
Change-Id: I496764f18b4c1ae0fa1a828dd7a90e937a42d41b
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- Move all static information from setup.py to newly added
pyproject.toml
- Add setup.cfg used for static information that cannot be added to
pyproject.toml due to it still being in beta.
- Modify mlw_codec to to throw a real python exception when importing
NumPy arrays instead of just printing them to stdout.
- Surround mlw_codec import with try catch statement to catch NumPy C
API mismatch errors and throw them again with a more detailed message.
- Update README.md with documentation about known issue with changing
used NumPy version after installing ethos-u-vela.
Change-Id: I1eeee5536be7c1744e30d6088f7069fbb1403e06
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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Reinstate constraint for stride height to (1,3) instead of (1,4) for
Conv2D and update unit tests.
Change-Id: I17389ee040eeff0cea08279cab1c038e951569ea
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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- Additional overflow checks are performed when running under
Microsoft Windows compared to Linux. These checks happen when
converting from Python int to NumPy int/uint
- The problem is that the lut activation values are int32 type,
however they are defined as Python ints. If these are converted to
numpy.int32 it could result in an overflow error
- The fix is to convert these values to uint32 but keep the
operator's IFM tensor type the same (as this will allow them to be
interpreted correctly)
- Fixing this highlighted another problem where convert_to_lut
always calls create_lut_tensor() with an int8 datatype, whereas it
should be using the IFM datatype
Change-Id: I781a9d850f654267aa4a67754438607c4bb95685
Signed-off-by: Tim Hall <tim.hall@arm.com>
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* Extend stride range from (1,3) to (1,4)
* Add stride 4 support when optimising CONV_2D
* Add some tests for various strides
Change-Id: Iddaeb42c4a6e02695ecdd3740bc8b9dd59a7eb3c
Signed-off-by: Raul Farkas <raul.farkas@arm.com>
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- An assert in Vela is triggered when the number of splits does
not evenly divide the input.shape[axis] value and the split offsets
are calculated wrongly.
- The fix is to add the same constraints as in the reference kernel
and only run the Split op on the NPU when the criterias are fulfilled.
- Modified test to reflect the new constraints
- Updated SUPPORTED_OPS.md
Change-Id: I4103ff4a3fdf9a813f5fcb7f51081b859e611100
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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This reverts commit 9d254b6f9e76ccf266a0f72a0171e73bc8d435c9.
Reason for revert: Due to 0-size constants being treated differently (MLTOOLS-2043)
Change-Id: Ie1150fb2dd9092050a7fd44708a893d52ffe59f8
Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
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Updated FlatBuffers autogenerated files to TensorFlow 2.11
Change-Id: Ied60f9fbacdcf91ec8d289cafbde0d88169bb349
Signed-off-by: wilisa01 <william.isaksson@arm.com>
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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- The issue is due to undefined behaviour when casting a NumPy float
to a NumPy unsigned integer which occurs in create_const_tensor()
- The fix is to make sure that the values are first cast to a Python
float
- In addition, the values datatype argument has been removed from
create_const_tensor() to stop the tensor and values datatypes getting
out of sync
Change-Id: I134b9be8c941b361929a5ae7db8cb35f2e9728f2
Signed-off-by: Tim Hall <tim.hall@arm.com>
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- Previously a feature was added in order to reduce SRAM usage
when optimizing for Size. An investigation has now been done
that shows that this feature is also beneficial when optimizing for
Performance and hence this patch removes the Size only limitation.
Change-Id: I5b130db43cbda47e09d4196ab1daa5a21e35ae00
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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Fixed an assert that was caused by a model that has a reshape operator
followed by another reshape operator. This structure has never been
thought of. However, since there is no need for the first reshape just
remove it from the path while traversing the graph.
Change-Id: I2a939df37502028ffc07115ac87e85375484efee
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- The uncascaded SRAM usage for an op in the cascade builder did not
take into account that OFM will be reusing the IFM for elementwise ops
and resulted in wrong values for the uncascaded memory.
- Changed code to use the _estimate_sram_usage since this
function does the calucation correctly.
Change-Id: I681bcf6e45ee869bbfb92306869b18ee4a838325
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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Deprecation of some data type aliases in NumPy version 1.24.0 caused Vela
to crash when using Python version 3.8 or above. Replaced the deprecated
aliases.
Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
Change-Id: Ide167ee864a340194ec5e69537c8718192c78ace
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- Fixed a problem where buffered weights were only used
in the first stripe that was produced. The following stripes
read the weights from permanent storage.
Change-Id: I176909fa0e2edbecf80e8ec8ac136f42d5d3bcd4
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- When operators are cascaded, there are rolling buffers
used between the producer and the consumer operator.
Depending on the attributes, like strides, there was a use
case when the allocated intermediate buffer was too small
and resulted in a buffer overflow. The problem was that
the producer ofm stripe width was greater than the consumer
ifm stripe width.
- Changed the allocation to use the max of the producer width
and consumer width
Change-Id: I5aa20795eac5591d254b2163deec329cf9325a1b
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
Change-Id: I026facce572ddce4249e05529f2bb1d285552ab9
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IFM's in persistent memory should not be included in the memory
op SRAM calculation.
Change-Id: Iaac4d2ad8b206c5fb727e5815477cb3611a13e0e
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- When introducing the support for reversed operands the npu performance
was not updated. The result is larger numbers (degrade) from the performance
estimater compared to the previous release. In reality there is no degrade
and the real performance is the same.
- Updated npu performance to reflect the behavior implemented by the
reversed operands attribute.
Change-Id: I1b37a07f25def8f7a8adbdaadcf931bfe49165cb
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- Only 1D bias shape is supported
- Modified test to reflect the constraint
- Update SUPPORTED_OPS.md
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
Change-Id: I00ae4b229d5f89512cb94f87f276af61cc66a6fd
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- The cascade builder estimates how much SRAM usage an operator
takes when calculating the cascades. If an elementwise operator
is included in a cascade the IFM2 will always be a constant/scalar
and the IFM2 will be in permanent memory and the size of the
IFM2 should not be included in the SRAM estimate.
- The scheduler did not take into account that IFM can be reused
for the OFM when calculating the op memory usage resulting in
a negative number for non-local memory usage. Corrected the
calculation and added assert to detect future problems.
Change-Id: Id7ec8fe1ec5560290f34579a7b9203a75067aba2
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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Investigated all code linter output and fixed non-intentional
reports.
Change-Id: If49d6df8fe1a8a6ae4f1e28de4889a8c5763a0b3
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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Added references to performance CSVs and documented per-layer performance.
Also removed a space that caused black in pre-commit to fail.
Change-Id: Ia20cb381654cc6344c68bcaad0a7dfc517d55e63
Signed-off-by: wilisa01 <william.isaksson@arm.com>
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- Adds missing operators and type conversion recording to DebugDB
Change-Id: If76b0b430bbe73ae1469024c3160ecf0eea26abe
Signed-off-by: wilisa01 <william.isaksson@arm.com>
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- Update copyright notices to use SPDX format and add OSS mail as contact.
- Update years on files where it had been missed.
Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
Change-Id: I7e9715ea4e17b76252728c708e46df12ad67ab1f
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- Added graph optimisation pass to support dilations greater than 2
in either dimension
- Removed supported operators restrictions
- Removed erroneous dilation on TRANSPOSE_CONV
- Updated unit tests and documentation
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ide302374b0d5eff25c20501383a63f6aa7625c52
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- Removed unused variable total_npu_weights to fix summary csv error
Change-Id: Id3c94166a787d2bb094ac6c6612fc866811515c2
Signed-off-by: wilisa01 <william.isaksson@arm.com>
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- Fixed the reporting of the input network operator to correctly
report the original operator type rather than the current one
- Fixed a divide by zero bug when calculating percentages
- Refactored the verbose-performance code so that console and csv
outputs use a single definition of the header and data
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ibd3fa99b65f0602dcdcff696f2d565ac13453306
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Fixed by adding an operation to copy the statically optimised
data to the subgraph output.
Change-Id: Ica757e37d5460237973444ffd39c7d2850f319e3
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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The reference kernel for the MEAN operator has changed.
As a result, the mean implementation can be simplified
and the constraint for mean int8 can be removed.
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
Change-Id: I318e9b495eefea99e7ac4aea4b8c436c83753405
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- A bug was introduced by using the original_shape attribute that
causes CPU CONV2D ops to fail to run due to an incorrect weight
tensor shape
- This was due to the original_shape not being modified when a
transpose was performed on the weight tensor
- The fix was to transpose the original_shape just like the current
shape
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ied72316463d26c502cf931b9dd5784041c42ab66
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- CPU side always needs to work we the original tensor shape.
Due to a bypass memory optimization the IFM, produced by CPU,
was stored with the wrong shape in the optimized file.
- Store the original tensor shape so it can be correctly
written to the optimized file.
Change-Id: I666dbcb0acd806ad208c0f925a51dfc25421688b
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
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- The previous patch the always replaced ifm with ofm
introduced unnecessary avg pool ops for some cases.
That patch has been reverted and this is a new solution.
- Replace ifm with ofm for the following condition:
a) Ops that are dependent that the original ifm tensor
shape is not changed by the bypass memory op function.
b) When the memory op has different IFM and OFM rank.
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
Change-Id: I16a023e169ae64c5db46f6f88516a5e1ca7ed7ef
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This reverts commit 5060ff53f5ac2382e04a68d7772bd71a36f63845.
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
Change-Id: I8dd7e9ed8325fd2e8c17509fd9757292706f5ee7
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Always make sure the bias is a 1D tensor.
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
Change-Id: Ic0cb85d4fb9d2e07b4d1b7ac6059bffa432e28a3
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- Due to a SPLIT op the following ADD op did get an IFM shape
that is bigger than its original shape but that is handled
by read_offset and read_shapes. The problem was that
the IFM was considered not be primary and an erroneously
swap was done.
- Make it even more clear when the swap is allowed.
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
Change-Id: I0aefa04234f66c935f269267ae8ed1d77da64c81
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Corrected offset calculation for operator Slice. All values
in tensor begin and tensor size must be used to calculate the
offset range in order to read the correct data.
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
Change-Id: Ic463d8f72a2167f8129109b8dcf005f034cce6ed
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- Remove very long live ranges that are standing out compared to
its neighbors. This can be seen on large networks with complex
structure. If they are chosen instead of shorter live ranges,
it will be difficult for the HillClimb Allocator to find a perfect
fit in the final allocation.
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
Change-Id: I6cf23adfdc06c1e93e12e9cf816453d940ff31f7
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- Refactored erroneously if statement that allowed illegal
swapping between ifm1 and ifm2 for elementwise operators.
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
Change-Id: Iec571f710824432edac9104d960f199f33a1b241
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- The algorithm for trying out different stripes in order
to optimize a sub schedule/cascade, have a problem that it
can split the initial cascade into several smaller cascades.
The problem with this is that it will increase IFM/OFM DRAM
bandwith and performance will drop.
- Changed the stripe algorithm to prefer long cascades.
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
Change-Id: I4f38b381597b7094819e9dd463aa1876e4e6bc62
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