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2021-04-30MLBEDSW-4350 Use padding instead of skirt for merged SplitSliceHenrik G Olsson
When the operations are merged some later passes are confused by start and end coordinates for the convolution not being along the edges of the IFM, and omitting padding. But we need the zero padding to keep the output the same as before the transformation. Also fixes bug where Vela could crash if convolution had explicit start coordinate. Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com> Change-Id: I8449d237350d528f83738b2f09124f1ed79c07ca
2021-04-29MLBEDSW-4501: Support MEAN single axis variationDwight Lidman
When a MEAN operator with a single reduction axis specifies the axis index attribute as an array with a single element rather than a scalar index, the operator is placed on the CPU even though it is technically supported. This commit fixes this issue and also adds some new tests for the axis constraints. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Ia287f3b9cc80a805e972cd4b2962e52526a8dc16
2021-04-21MLBEDSW-4413: MobileNet V3 regressionDwight Lidman
This commit resolves a recent regression in multiple networks (including MobileNet V3). The regression was caused by a recent change to IFM block size calculation where a term mistakenly left out (due to it missing from the spec). The IFM microblock size has been amended for the Ethos U-55 128 config and the block size calculations now use these sizes instead (although equivalent with OFM microblock sizes). Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Ic504b4becd6c3a26334a7275189d78ff0fe2cf69
2021-04-19[MLBEDSW-4421] Fix verbose-all crashFredrik Svedberg
Fixed exception when using the CLI option --verbose-all. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I203fe31ad6914936730343958009e2370045c67c
2021-04-19[MLBEDSW-4414] Fix verbose-operators for multiple custom opsFredrik Svedberg
Fixed exception for --verbose-operators option when there are multiple custom operators in the network. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I5ab743d96a4e0367818fbe46cc47896c691d888c
2021-04-16MLBEDSW-4132 Fix off-by-one error for negative packing axisHenrik G Olsson
Also applies to unpack. Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com> Change-Id: I07e7083aeb6aefd6e26f9d134b858080f28f1719
2021-04-16MLBEDSW Vela: Fix check for format restrictionsPatrik Gustavsson
Fixed the check related to if there are any CPU producers/consumers. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I0ed08c650d1ca34e8e148aee68a5ed09c25fdd87
2021-04-16MLBEDSW-3550 Only use simple scaling when bitexact with TFLiteHenrik G Olsson
For 8 bit arithmetic we cannot guarantee reproducibility in the general case since precision differs, affecting rounding near half integers. It should be safe when the ratio between output and input scales has its 12 LSBs all set to 0, however. For 16 bit arithmetic it should be sufficient to adjust the input and output scalings with a factor of 2 to get the same rounding. Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com> Change-Id: I809c0042615d16c5488d61f0c7d88e1a1315e6eb
2021-04-15MLBEDSW-4397 Fix Reshape ifm/ofm prod/cons by cpu opPatrik Gustavsson
Not only the sg input outputs need to be considered before removing Reshape. Added check if Reshape ifm/ofm is produced respectively consumed by CPU. Handling is the same as if tensor is sg input/output. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: If509e1d23e3f22ed4c963d8dabd8c00c6b9c07e3
2021-04-14MLBEDSW-4103: Block config calc updateerik.andersson@arm.com
The previous calculation of the IFM block height and width yielded incorrect block configs when running transpose_conv networks with certain hardware constraints. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: I8b6936a3e8c37da640bdeac84ecfea8363f910f9
2021-04-09MLBEDSW-4073 Handle elementwise ops with same tensor for both inputsHenrik G Olsson
Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com> Change-Id: I0e6bb46b7b91ed10f5bda34fba66d8b714560f47
2021-04-08Fix stats_writer.py exceptionFredrik Svedberg
Fixed exception in stats_writer.py. Change-Id: I625390aec185345cadd0d8fa5edb66907b9be242 Signed-off-by: Fredrik Svedberg <Fredrik.Svedberg@arm.com>
2021-04-08MLBEDSW-4334 Non-linear format decision in graph opt.Patrik Gustavsson
Check if non linear tensor format can be used is refactored. -Flag avoid_NHCWB16 replaced with needs_linear_format -Checking restrictions located to one function in graph optimiser. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Iec5c7996a1a6039cad052197f1ae56f7c0290440
2021-04-07MEAN implementation changed to Average PoolDwight Lidman
This is a small commit which changes one of the four MEAN implementations to a simpler one, using an AvgPool instead of a DepthwiseConv. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I9e8af071e8b820796577ee4792b4812a1212602b
2021-04-06MLBEDSW-4249 Hide stack traces in error messagesHenrik G Olsson
When faced with an invalid tflite file we now catch the exception to make it clear to the user that the issue is with the input and not with Vela, instead of just crashing. Same also applies to our own Vela error messages. Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com> Change-Id: I56a81c5be9e1f46f3b98a88c6d24ee42fa0e450d
2021-03-31MLBEDSW-4286: Bug fix Concat using IFM streamingLouis Verhaard
IFM box calculation was wrong because 2 variables were referencing/updating the same list. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: Ibed4e94c474682e14a6dd898029f14af11c9479a
2021-03-31MLBEDSW-3461: Check configuration SRAM sizeLouis Verhaard
Added check that configured SRAM size is within bounds. Change-Id: I5dce3df0788f2b00402e9a541bad11612fa19463 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-03-31Handle absent weights_compression_ration when printingHenrik G Olsson
Change-Id: Iafb31af73d80adcc901b241c34dda78be360bc14 Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
2021-03-31MLBEDSW-3502: Bug fix addresses >= 32 bitLouis Verhaard
Bug fix in generation of register command offsets that do not fit in 32 bit. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: Iabb99cf6536c0f77b934691f8744df61f1eab3ed
2021-03-30Performance improvement in tensor allocationLouis Verhaard
- Tensor allocation verification was O(N^2), is now closer to O(N) - Removed a sort in HillClimb allocator Change-Id: I286a269881490c485cc2b0eeab3b1ecffa8f3df0 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-03-30MLBEDSW-4219: Add tensor allocation info to summaryerik.andersson@arm.com
Added the theoretically minimum max memory usage and the allocator overhead to the Vela summary. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: If373dfeaac50d6f8b56554d435bf22af2c3acda3
2021-03-26MLBEDSW-4163: OFM zero point outside valid rangeDwight Lidman
This commit fixes a bug where the OFM zero point would assume values outside of [0, 255] due to it's usage as a stand-in for a bias when emulating the TensorFlow Lite implementation of MEAN. The solution is to adjust for the bias using an ADD operator with the bias value as an int16 const tensor. The 16-bit integer is needed as the bias is 32 bits in the original implementation but can effectively assume values in the range [-255, 255]. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I84df48ea89bb559954f1b2c289b65e08a6418274
2021-03-25MLBEDSW-4071: Power of two handling 16-bit tanh/sigmoidLouis Verhaard
Added special handling of power-of-two input scales for 16-bit tanh/sigmoid to align with the reference. Change-Id: I87831bcd587623d7db7100e768905355c2c98e9d Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-03-22MLBEDSW-3502: Add address checksLouis Verhaard
Added checks during command stream generation to make sure that address boundaries are respected. Change-Id: I4dbc693b42d54e35c8fcc785e8be88059e409eec Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-03-19MLBEDSW-3458: Added command stream size check.erik.andersson@arm.com
If the command stream size exceeds a certain threshold, a VelaError will now be raised. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: I9b9383f4c298a778b160cd527374e9244e4cae26
2021-03-19Address generation fixMauricio Briceno
- The architecture supports address extensions wider than 32b via the cmd1.param Change-Id: I7a01b4596f7a54f6be05b8e2c454494e6751757b Signed-off-by: Mauricio Briceno <mauricio.briceno@arm.com>
2021-03-16MLBEDSW-4215: Add support for MEAN to match QuantizedMeanOrSum implementationDwight Lidman
This commit adds support for emulating the behavior of the QuantizedMeanOrSum implementation of MEAN in TensorFlow Lite. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Ifd24e0e678e2f85cd66ab82deeaaf010d5351b1e
2021-03-16MLBEDSW-4223: Full support for PAD operatorLouis Verhaard
- Added full support for PAD operator - Hardware padding is still used whenever possible - Bug fix Pad followed by max pool if IFM contains negative values Change-Id: Ifc64d1943737d94466f5e2821009dab12a49a965 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-03-12MLBEDSW-4070: Addresses errors with the LeakyReLU operator.erik.andersson@arm.com
LeakyReLU IFMs will now have unique addresses and the alpha tensor will have correct scaling. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: If94fa91a0b61175309ac450bf6b38a63362780ab
2021-03-09MLBEDSW-4209 Use live range alignment when allocatingHenrik G Olsson
Change-Id: I05216cebe785a3669032a3f021a9b496c44c4d66 Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
2021-02-25MLBEDSW-1499: Add MEAN operatorDwight Lidman
This commit adds support for the MEAN operator, with some caveats. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I165cb26cb5aefd68e70d2cfc68291ccf7b778921
2021-02-25MLBEDSW-3571: Sum and FC should not crash when asking for keep_dims.erik.andersson@arm.com
Previously the keep_dims or keep_num_dims attribute was not supported for Sum and Fully Connected operators and would thus crash for certain tests. With this update, the attribute is extracted correctly and saved to the optimised tflite file. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: If33487f6d299bb99788bb3d13332b842ba961641
2021-02-25MLBEDSW-4064: Update copyright headerserik.andersson@arm.com
All files which have been updated in 2021 and contain a copyright header have had their headers updated. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: Ia682111a719d16e690433398ccfb69c7e93c1cd1
2021-02-17MLBEDSW-4022: support PAD followed by pool operatorLouis Verhaard
PAD followed by max/average pool is run on NPU if NPU padding can be used. Average pool is converted to depthwise. Change-Id: Icc3652e6d9ecff5ac3dc7d92080313d90c245404 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-02-17[MLBEDSW-3813] Fix LSTM operator pass throughFredrik Svedberg
Fixed pass through of LSTM operator. Change-Id: I23140c69ab6cdc83f6bb8129256b4cc6a7c5ffac Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2021-02-16MLBEDSW-4076 Fix read_offset at create_primary_opPatrik Gustavsson
Fix read_offset at create_primary_op The read_offset need to be copied when adding avg pool as primary operator. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I6f168517a0e22543455b623b6b4f59237e8d530a
2021-02-16Make HillClimb allocation reproducibleFredrik Svedberg
Made HillClimb allocation results reproducible between runs. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I0535947e9cd9c6e0cf896e81b127d93cab54ebc8
2021-02-16Corrected the help string of --force-block-configJacob Bohlin
Made the same correction in OPTIONS.md Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: If79ee5c4c7464b40a72bbe6871b52a9eb0b308e1
2021-02-12MLBEDSW-3808: Ported search allocator to python2.1.0.rc1Louis Verhaard
- Straight port of the C++ implementation to python. - Renamed the allocator from "Search" to "HillClimb" Change-Id: I50797d541f326d0264daf79bf7866aef32350a60 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-02-12MLBEDSW-3509: Updated the debug database to support multiple custom operators.erik.andersson@arm.com
Previously the debug database lost some operators in the debug database outputs when multiple custom operators were generated by Vela. Also, the file offsets for command streams were always 0, even for a single custom operator. This patch should rectify these problems. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: Ieb072440d4f1806d4833a676683b4f42f431f3df
2021-02-12MLBEDSW-3902: Fixes invalid op when cloning LeakyReLU operatorerik.andersson@arm.com
When running specific networks containing LeakyReLU operators, Vela would crash when cloning an ofm of a LeakyReLU operator. In this procedure a deepcopy usage would try to copy an OperatorInfo object, which caused an error. This was fixed by replacing the deepcopy usage with a copy and then manually referencing new instances of sensitive variables. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: I46917858896fbdf52245dac6c6d9c18bc7ecdd0d
2021-02-12MLBEDSW-3600: Cascading support for ResizeBilinearJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I7899263ff5bb3d0de00681ee8351a02eecff1553
2021-02-11MLBEDSW-3774 Fix avoid cascading for spillingPatrik Gustavsson
Fix avoid cascading for spilling. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: If86189bd1566eaa14387dfc2c02e3324ea6c184e
2021-02-11MLBEDSW-3774 Remove SplitSliceReadPatrik Gustavsson
Removed SplitSliceRead from subgraph during graph optimisation. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I9315d4c2a6767828dd2b4e66823d73b10ebee99c
2021-02-09MLBEDSW-3774 Removed ConcatSliceWritePatrik Gustavsson
-Removed ConcatSliceWrite from the optimised graph. Always executed as avgpool, which is equivalent with before the patch. -Added copy op to enable more removal of reshapes. Sg input/outputs need to remain. When Reshape input and outut, are sg input/outputs a copy op is needed to be inserted, in order to remove the reshape. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Id7be9966673ae34499e8518a5544104493fe326b
2021-02-08MLBEDSW-3937 Fix check for NHCWB16 for FCPatrik Gustavsson
Fix check for NHCWB16 for modifying FC input. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ie50c32ca079afadd0af9b7b909820794ceee373c
2021-02-08MLBEDSW-3953: Output diff in mobilenet_v3Diqing Zhong
Fixed two issues: - Cmd stream can be out of order in Ifmstreaming - In H32, LUT could be corrupted if blockdep is not 0 Change-Id: I2edd84429b93d83b2794f14937ce3fd279fd4a24 Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2021-02-05MLBEDSW-3771: Updated to TF 2.4 flatbuffer schemaTim Hall
Updated tflite loader and mappings from tensorflow 2.3 to tensorflow 2.4 Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I55884000ee139baf639bb0377008e0534f72fe94
2021-02-05vela: Change Shape4D mutability usageTim Hall
- Removed requirement for cloning shapes when unique values required by forcing top-level immutability. This alleviates issues with Shapes being unintentionally shared and then mutated as if value-types. - Shape4D fields can no longer be assigned without replication. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ic0dbfa349eb0215eabefb4f4e2cf99f12d83699c
2021-02-05MLBEDSW-3772 Removed fixup_act_reorderPatrik Gustavsson
Removed fixup_act_reorder from graph optimisation. As Reshape ops has been removed this optimization should not be needed. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I2c375ee7787bf15f66c1e16514ed62727934d869
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