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This commit fixes a regression caused by a recent
commit where io_ranges and elementwise_broadcast
were failing with off-by-one errors.
The culprit was the incorrect usage of NATURAL
rounding in cases of elementwise ADD and SUB
where the input and output scales were equal and
advanced scaling was not used.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I35d56298e911a4d1bbca7d201bcde6044c8a5490
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A recent fix to another MEAN bug introduced a new
bug. The bug was due to some incorrect logic for
checking the axis attribute.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I65d3486a12e029f7c4450074f03fcd1974f65d8a
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When the operations are merged some later passes are confused by start
and end coordinates for the convolution not being along the edges of
the IFM, and omitting padding. But we need the zero padding to keep
the output the same as before the transformation.
Also fixes bug where Vela could crash if convolution had explicit
start coordinate.
Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
Change-Id: I8449d237350d528f83738b2f09124f1ed79c07ca
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When a MEAN operator with a single reduction axis
specifies the axis index attribute as an array with
a single element rather than a scalar index, the
operator is placed on the CPU even though it is
technically supported.
This commit fixes this issue and also adds some new
tests for the axis constraints.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Ia287f3b9cc80a805e972cd4b2962e52526a8dc16
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This commit resolves a recent regression
in multiple networks (including MobileNet V3).
The regression was caused by a recent change to
IFM block size calculation where a term mistakenly
left out (due to it missing from the spec).
The IFM microblock size has been amended for the
Ethos U-55 128 config and the block size calculations
now use these sizes instead (although equivalent with
OFM microblock sizes).
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Ic504b4becd6c3a26334a7275189d78ff0fe2cf69
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Fixed exception when using the CLI option --verbose-all.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I203fe31ad6914936730343958009e2370045c67c
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Fixed exception for --verbose-operators option when there are
multiple custom operators in the network.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I5ab743d96a4e0367818fbe46cc47896c691d888c
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Also applies to unpack.
Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
Change-Id: I07e7083aeb6aefd6e26f9d134b858080f28f1719
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Fixed the check related to if there are any CPU
producers/consumers.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I0ed08c650d1ca34e8e148aee68a5ed09c25fdd87
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For 8 bit arithmetic we cannot guarantee reproducibility in the general
case since precision differs, affecting rounding near half integers.
It should be safe when the ratio between output and input scales has
its 12 LSBs all set to 0, however.
For 16 bit arithmetic it should be sufficient to adjust the input and
output scalings with a factor of 2 to get the same rounding.
Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
Change-Id: I809c0042615d16c5488d61f0c7d88e1a1315e6eb
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Not only the sg input outputs need to be considered
before removing Reshape.
Added check if Reshape ifm/ofm is produced respectively
consumed by CPU. Handling is the same as if tensor is
sg input/output.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: If509e1d23e3f22ed4c963d8dabd8c00c6b9c07e3
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The previous calculation of the IFM block height and width
yielded incorrect block configs when running transpose_conv
networks with certain hardware constraints.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: I8b6936a3e8c37da640bdeac84ecfea8363f910f9
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Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
Change-Id: I0e6bb46b7b91ed10f5bda34fba66d8b714560f47
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Fixed exception in stats_writer.py.
Change-Id: I625390aec185345cadd0d8fa5edb66907b9be242
Signed-off-by: Fredrik Svedberg <Fredrik.Svedberg@arm.com>
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Check if non linear tensor format can be used is
refactored.
-Flag avoid_NHCWB16 replaced with needs_linear_format
-Checking restrictions located to one function in graph optimiser.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Iec5c7996a1a6039cad052197f1ae56f7c0290440
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This is a small commit which changes one of
the four MEAN implementations to a simpler
one, using an AvgPool instead of a
DepthwiseConv.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I9e8af071e8b820796577ee4792b4812a1212602b
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When faced with an invalid tflite file we now catch the exception to
make it clear to the user that the issue is with the input and not with
Vela, instead of just crashing.
Same also applies to our own Vela error messages.
Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
Change-Id: I56a81c5be9e1f46f3b98a88c6d24ee42fa0e450d
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IFM box calculation was wrong because 2 variables were
referencing/updating the same list.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: Ibed4e94c474682e14a6dd898029f14af11c9479a
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Added check that configured SRAM size is within bounds.
Change-Id: I5dce3df0788f2b00402e9a541bad11612fa19463
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Change-Id: Iafb31af73d80adcc901b241c34dda78be360bc14
Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
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Bug fix in generation of register command offsets that do not fit in 32 bit.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: Iabb99cf6536c0f77b934691f8744df61f1eab3ed
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- Tensor allocation verification was O(N^2), is now closer to O(N)
- Removed a sort in HillClimb allocator
Change-Id: I286a269881490c485cc2b0eeab3b1ecffa8f3df0
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Added the theoretically minimum max memory usage and
the allocator overhead to the Vela summary.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: If373dfeaac50d6f8b56554d435bf22af2c3acda3
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This commit fixes a bug where the OFM zero point
would assume values outside of [0, 255] due to it's
usage as a stand-in for a bias when emulating the
TensorFlow Lite implementation of MEAN.
The solution is to adjust for the bias using an
ADD operator with the bias value as an int16 const
tensor. The 16-bit integer is needed as the bias
is 32 bits in the original implementation but can
effectively assume values in the range [-255, 255].
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I84df48ea89bb559954f1b2c289b65e08a6418274
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Added special handling of power-of-two input scales for
16-bit tanh/sigmoid to align with the reference.
Change-Id: I87831bcd587623d7db7100e768905355c2c98e9d
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Added checks during command stream generation to make sure
that address boundaries are respected.
Change-Id: I4dbc693b42d54e35c8fcc785e8be88059e409eec
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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If the command stream size exceeds a certain threshold,
a VelaError will now be raised.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: I9b9383f4c298a778b160cd527374e9244e4cae26
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- The architecture supports address extensions wider than 32b via the cmd1.param
Change-Id: I7a01b4596f7a54f6be05b8e2c454494e6751757b
Signed-off-by: Mauricio Briceno <mauricio.briceno@arm.com>
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This commit adds support for emulating the behavior
of the QuantizedMeanOrSum implementation of MEAN in
TensorFlow Lite.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Ifd24e0e678e2f85cd66ab82deeaaf010d5351b1e
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- Added full support for PAD operator
- Hardware padding is still used whenever possible
- Bug fix Pad followed by max pool if IFM contains negative values
Change-Id: Ifc64d1943737d94466f5e2821009dab12a49a965
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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LeakyReLU IFMs will now have unique addresses
and the alpha tensor will have correct scaling.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: If94fa91a0b61175309ac450bf6b38a63362780ab
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Change-Id: I05216cebe785a3669032a3f021a9b496c44c4d66
Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
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This commit adds support for the MEAN operator,
with some caveats.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I165cb26cb5aefd68e70d2cfc68291ccf7b778921
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Previously the keep_dims or keep_num_dims attribute was not supported for Sum and Fully Connected operators and would thus crash for certain tests. With this update, the attribute is extracted correctly and saved to the optimised tflite file.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: If33487f6d299bb99788bb3d13332b842ba961641
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All files which have been updated in 2021 and contain a copyright header have had their headers updated.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: Ia682111a719d16e690433398ccfb69c7e93c1cd1
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PAD followed by max/average pool is run on NPU if NPU
padding can be used. Average pool is converted to depthwise.
Change-Id: Icc3652e6d9ecff5ac3dc7d92080313d90c245404
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Fixed pass through of LSTM operator.
Change-Id: I23140c69ab6cdc83f6bb8129256b4cc6a7c5ffac
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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Fix read_offset at create_primary_op
The read_offset need to be copied when adding
avg pool as primary operator.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I6f168517a0e22543455b623b6b4f59237e8d530a
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Made HillClimb allocation results reproducible between runs.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I0535947e9cd9c6e0cf896e81b127d93cab54ebc8
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Made the same correction in OPTIONS.md
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: If79ee5c4c7464b40a72bbe6871b52a9eb0b308e1
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- Straight port of the C++ implementation to python.
- Renamed the allocator from "Search" to "HillClimb"
Change-Id: I50797d541f326d0264daf79bf7866aef32350a60
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Previously the debug database lost some operators in the debug database outputs when multiple custom operators were generated by Vela.
Also, the file offsets for command streams were always 0, even for a single custom operator. This patch should rectify these problems.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: Ieb072440d4f1806d4833a676683b4f42f431f3df
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When running specific networks containing LeakyReLU operators, Vela would crash when cloning an ofm of a LeakyReLU operator.
In this procedure a deepcopy usage would try to copy an OperatorInfo object, which caused an error.
This was fixed by replacing the deepcopy usage with a copy and then manually referencing new instances of sensitive variables.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: I46917858896fbdf52245dac6c6d9c18bc7ecdd0d
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Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I7899263ff5bb3d0de00681ee8351a02eecff1553
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Fix avoid cascading for spilling.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: If86189bd1566eaa14387dfc2c02e3324ea6c184e
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Removed SplitSliceRead from subgraph during
graph optimisation.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I9315d4c2a6767828dd2b4e66823d73b10ebee99c
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-Removed ConcatSliceWrite from the optimised graph.
Always executed as avgpool, which is equivalent with
before the patch.
-Added copy op to enable more removal of reshapes.
Sg input/outputs need to remain. When Reshape input and
outut, are sg input/outputs a copy op is needed to
be inserted, in order to remove the reshape.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Id7be9966673ae34499e8518a5544104493fe326b
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Fix check for NHCWB16 for modifying FC input.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ie50c32ca079afadd0af9b7b909820794ceee373c
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Fixed two issues:
- Cmd stream can be out of order in Ifmstreaming
- In H32, LUT could be corrupted if blockdep is not 0
Change-Id: I2edd84429b93d83b2794f14937ce3fd279fd4a24
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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Updated tflite loader and mappings from tensorflow 2.3 to tensorflow 2.4
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I55884000ee139baf639bb0377008e0534f72fe94
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