Age | Commit message (Collapse) | Author |
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- Changed Ethos-65 AXI port address width from 48 to 40-bits
- Fixed the use of arena_cache_size in mem_type_size() to cover the
arena as well as the cache memory area
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I826462a0cbd0c061cccbc7c83dde446778a2b1ca
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- Merged dev/scheduler at 83639f90e8c828f70de6e29142355a940224959b
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I0050529d4b42da93768c7264296434dd877fb5b4
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Bug fix in generation of register command offsets that do not fit in 32 bit.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: Iabb99cf6536c0f77b934691f8744df61f1eab3ed
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Added checks during command stream generation to make sure
that address boundaries are respected.
Change-Id: I4dbc693b42d54e35c8fcc785e8be88059e409eec
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Moved blockdep calculation and other helper functions for
code generation to a separate file.
Change-Id: I2f8ccea478654272ebf42217fc5c1800e9ad177a
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Added public API function npu_find_block_configs.
Change-Id: Ib0925a62d7c5d19a9b9fbd8d808943c2ea2df02f
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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All external APIs are now exposed by api.py.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: I33f480e424692ac30e9c7d791f583199f31164a7
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Added external API to generate register command streams.
Existing code generation has been refactored to make
use of this API.
Change-Id: Ibb4c2b167809869f16470b14da24f08a65c82b7b
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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