Age | Commit message (Collapse) | Author |
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- Use non local memory as the base sram usage for a subgraph
- Make avoid_for_spilling more generic for all mem configs
Change-Id: I99cd30fe6a8ba075d5a70dc2138aa0635afaadb3
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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Added a static class TensorAddressMap that stores all Tensor addresses
based on their equivalence_id. Made the "address" field into a property
which getter and setter looks up/sets the tensor's address in
TensorAddressMap.
This makes the references to cpu_tensor/npu_tensor obsolete and they
have been removed.
Addition to scheduler: avoid SRAM spilling if an op has consumers in
other subgraphs.
Minor rework in LUTState; it will now assign a unique equivalence_id to
the SHRAM lut tensor to avoid issues with addressing. The equivalent
checks in LUTState now compares the values of the LUT instead of the the
equivalence_id.
Updated LUT unit tests accordingly.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I41de5a8a4e5f07b77d6544d8d4034b754993e503
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- Processing reshapes at the end of NPU subgraphs selected NHCWB16
tensor format before handing over to the CPU. This commit detects
end-of-subgraph during the reshape-consumers compatibility check
and chooses NHWC format instead.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ieefdbecdba1a6183d79d3ac4d2505503dbf321cb
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Added checks for not using NHCWB16 for reduce_sum int32 which makes
int8/uint8 softmax work.
Also enabled softmax graph rewrite by default and fixed a saturation
problem.
Change-Id: Ic01bd9ece7e5c3edb2900b7915cc747efe9e5760
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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- Reshapes that merely add/remove dimensions, rather than re-layout the
data need not fall back to NHWC. This commit allows reshapes betweeen
NPU operators to use NHCWB16.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ieb7745e586bf324e92e741a04b74caf7285f4b8b
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Added --weight-estimation-scaling, which enables
additional scaling of weight compression scale estimate.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Idcda41257f44901d3a3f345341e07fb1ae8585a9
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Avoid usage of NHCWB16 when Stack/Pack/Concat is performed in axis 3,
and the "concat start" of each slice to be combined is not a multiple
of 16.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: If3f7b4a3424be3c86fc2dc48e8649ce4c4f49485
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Avoid concat op as predecessor in ifm streaming,
when Sram spilling is to be applied.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I2ba6283a7561a12d54a06552a15e122bb082b7a1
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Added support for one more memory configuration-
Change-Id: Iac19992386e3e9b80bd519acb1b0a399c47d736f
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
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Additional supported memory configurations:
-Permanent_storage = DRAM
-Tensor arena either in DRAM or SRAM
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I20beb7151e306bfdba540e7c0b2a7b478b4d94e1
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- No functional change
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I5ab1198b9d092cd041fa9b85b2dee9900d299bfc
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Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: I92b18262608415e84266d2903e17fc5112793a38
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Make it configurable for using NHCWB16 between
cascaded passes.
Signed-off-by: Charles Xu <charles.xu@arm.com>
Change-Id: I259cdaa424d11ea38f17e671490ad1e630bbae44
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Also updated README.md
Change-Id: I118309c61f4d00e8508d6b888c606995490fba39
Signed-off-by: Diego Russo <diego.russo@arm.com>
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Use pre-commit framework [1] to run black and flake8 before the commit.
black and flake8 are managed by the pre-commit framework and they can be
run manually by the user using `pre-commit run` command.
Fix the code base with the help of black and flake8.
Fix import statements according to PEP8 guidelines [1]
Both tools have the following settings (specified in the pre-commit
configuration file):
* line length: 120 characters
* directory to exclude: ethosu/vela/tflite/ and ethosu/vela/ethos_u55_regs
Updated README.md on how to install pre-commit and how to run sanity checks.
Pipenv files have been updated including new dependencies for pre-commit.
[1]: https://www.python.org/dev/peps/pep-0008/#imports
[2]: https://github.com/pre-commit/pre-commit
Change-Id: I304d9fffdf019d390ffa396a529c8a7c2437f63d
Signed-off-by: Diego Russo <diego.russo@arm.com>
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Added support for using NHCWB16 between cascaded passes.
(For Reshape format is kept to NHWC)
Change-Id: I0ef1631984fec89fe09999b64ae69563e2aefc9b
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
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- Added modules ethosu.vela and ethosu.mlw_codec.
- Added README and various configuration files.
Change-Id: I3690f8c8f5966306ecddaeb2793c30ca9c6e2eee
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