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path: root/ethosu/vela/pass_packing.py
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2023-04-17MLBEDSW-7196 Add LSTM supportFredrik Svedberg
Added int8 and int16 UNIDIRECTIONAL_SEQUENCE_LSTM support. The implementation does not include support for: * CIFG * Peephole * Projection * Normalisation This change also: * Removed unused Op.BlockLSTM operation type. * Removed the only one consumer limitation on putting the SplitSliceRead on the tensor consumer(s), if all consumers fullfills the requirements * Added Op.VariableTensorWrite as a Operation.memory_function to make sure writes to variable tensors: * Always use linear mode * Are not moved to fast scratch * Are not fused with other elementwise operation tensor ranges Change-Id: Ief831738924ac3d1f2ba6d41f10bd6dc969911f3 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2023-03-14MLBEDSW-6260: Add support for using DMA to copy feature mapsJohan Alfven
- Reshape ops can be bypassed and there is no need to process them by the NPU. There are use cases when the IFM must be preserved so a memcpy is needed. This is implemented by an AvgPool. - In order to reduce the cost of the AvgPool the IFM can be copied by DMA. This is faster and also it can be turned into a real NOP in cases where the IFM and the OFM can use the same memory space. - Added new memcpy op. Only NHWC format supported since DMA can not change the format on the fly. - Allow ofm to reuse ifm for memcpy op - Make sure the DMA copy size is 16 byte aligned Change-Id: I3605a48d47646ff60d2bb3644dd3a23f872235a7 Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2023-03-10MLBEDSW-7386: Fix assert in pass packingJohan Alfven
- The assert was caused due to a faulty optimization being done in the pass packing when trying to group CPU passes. The code did not take into account that a CPU op could have many outputs. -The fix is to make sure that the pass the follows the CPU pass is not dependent on any of the outputs from the CPU pass. If there is a dependency the CPU pass cannot be moved. Change-Id: Ia0c90bae1ed97d503a97e7bc353f834a0fa75130 Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2023-02-14MLBEDSW-7316: Fix crash for networks with resource variablesJohan Alfven
- The problem was that networks with resource variables have not been thought of. The major problem was the graph traversal where these ops were not visited resulting in an empty subgraph that resulted in the crash. - Fixed the problem by attaching virtual tensors to the ops simulating subgraph output. These tensors are only used to get the graph traversal to work. - Fixed serializing of attribute container and shared_name - Fixed subgraph index for operator CallOnce - All resource variable ops are pushed to the CPU Change-Id: I815f9c81baf7a3fbb686e895980b462f58208b6e Signed-off-by: Johan Alfven <johan.alfven@arm.com>
2022-11-16MLBEDSW-6620: Update copyright notice and yearsRickard Bolin
- Update copyright notices to use SPDX format and add OSS mail as contact. - Update years on files where it had been missed. Signed-off-by: Rickard Bolin <rickard.bolin@arm.com> Change-Id: I7e9715ea4e17b76252728c708e46df12ad67ab1f
2022-07-23MLBEDSW-4157: Add RESIZE_NEAREST_NEIGHBOR supportTim Hall
- Changed ResizeBilinear to support ResizeNearestNeighbor as well for 1x1 IFM, IFM equal OFM, and non-align corners - Added support for ResizeNearestNeighbor with align corners by converting to a DepthwiseConv - Updated supported operator unit tests - Added is_resize() helper function and some associated refactoring Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Id5bdf2a25e8aa6a4f28b7236250abf768141ce37
2022-05-19MLBEDSW-6430: MLCE: Update to graph has sequential ethos-u opsJohan Alfvén
Update to the "Vela splitting network into two ethos operators" patch allowing the CPU pass to be moved last in the pass_list. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: I2e8a299101e5d65e963327bed7c8d891fff6523e
2022-05-18MLBEDSW-6430: MLCE: Vela splitting network into two ethos operatorsJohan Alfvén
- Due to how the graph is traversed, the final pass list contained unnecessary multiple Ethos-U operators. Functionality wise not a problem but it adds extra context switching between CPU and NPU. - By applying sorting rules to the pass list, it is possible to create a more optimal pass list that reduces the numbers of Ethos-U operator. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: Ib556f902e1f321b5c50238fada7aa92b9810b27a
2022-03-30Update version of Black to 22.3.0Jonas Ohlsson
Update version of Black to 22.3.0 due to updated dependencies. Updates to fix reported issues due to new version. Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com> Change-Id: I60056aae452093ce8dcea1f499ecced22b25eef1
2022-01-27MLBEDSW-6060: Revert patch for MLBEDSW-5582Johan Alfvén
- Issue was due to a previous patch to fix MLBEDSW-5582 - Revert fix for MLBEDSW-5582 commit 849ff81f82c10a68898e5101930b92372bec5565, - Made new fix for MLBEDSW-5582 that enforce output tensor from NPU graphs to be in NHWC format. This information is otherwise lost in the case when parts of a concatenation are placed in different custom operators resulting in mismatch bewteen NHWC and NHCWB16. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: Iab3ba29d348353c854f357836e6aa7c338ae1572
2022-01-24MLBEDSW-5582: MLCE: memory corruption with zero concatTim Hall
- This bug was due to an interaction between multiple Ethos-U custom operators and concatenation of constant tensors - It resulted in different parts of the concatenation being placed in different custom operators - The fix involves places all parts of the concatenation into the same custom operator by switching to a breadth first search in pass packing Signed-off-by: Johan Alfven <johan.alfven@arm.com> Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ic47613cfd7bf675b4674dc91d6f9765849ba3130
2021-12-17MLBEDSW-5834: split shape is None when split offset is notTim Hall
- This bug causes an exception to occur when trying to index split shape in Box.transform_with_strides_and_skirt() - The bug was due to the read shapes not being initialised when creating a primary op in pass packing Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I3ebd7fc4c7ef5c06488a36d8340a17ae6afd4609
2021-11-02MLBEDSW-5437: MLCE: Vela ignores back2back Activations in modelTim Hall
- Back-to-back 16-bit activation ops were packed into the same pass because there was no check to disallow it - The solution is to set the appropriate incompatible-flags Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Idb3c741a7b52e0d81c1f687f6ecf78352b7872dd
2021-07-09MLBEDSW-4839: Fix issues with Elementwise IFM/OFM overlapTim Hall
- Fixed typo with not using ifm.mem_type - Fixed bug with using ifm1 properties when only ifm2 is a potential match - Removed restriction on not considering SHL and SHR for overlap - Removed some dead reshape code Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Id9bcc3c2b3ee9ac7b6276187d3e2f513b4acd4b5
2021-05-27MLBEDSW-4034: New Scheduler Size or Performance OptimisationTim Hall
- Merged dev/scheduler at 83639f90e8c828f70de6e29142355a940224959b Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I0050529d4b42da93768c7264296434dd877fb5b4
2021-02-16MLBEDSW-4076 Fix read_offset at create_primary_opPatrik Gustavsson
Fix read_offset at create_primary_op The read_offset need to be copied when adding avg pool as primary operator. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I6f168517a0e22543455b623b6b4f59237e8d530a
2021-02-11MLBEDSW-3774 Remove SplitSliceReadPatrik Gustavsson
Removed SplitSliceRead from subgraph during graph optimisation. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I9315d4c2a6767828dd2b4e66823d73b10ebee99c
2021-02-09MLBEDSW-3774 Removed ConcatSliceWritePatrik Gustavsson
-Removed ConcatSliceWrite from the optimised graph. Always executed as avgpool, which is equivalent with before the patch. -Added copy op to enable more removal of reshapes. Sg input/outputs need to remain. When Reshape input and outut, are sg input/outputs a copy op is needed to be inserted, in order to remove the reshape. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Id7be9966673ae34499e8518a5544104493fe326b
2021-02-05vela: Change Shape4D mutability usageTim Hall
- Removed requirement for cloning shapes when unique values required by forcing top-level immutability. This alleviates issues with Shapes being unintentionally shared and then mutated as if value-types. - Shape4D fields can no longer be assigned without replication. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ic0dbfa349eb0215eabefb4f4e2cf99f12d83699c
2021-02-04MLBEDSW-3951 Consider reshaping in pass packingPatrik Gustavsson
Consider reshaping in pass packing, when desiding if operators can be packed. For the cases where there is a reshape between ops they cannot be fused. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I8f2833b3fff156e9633ce0189d1d0df9109a6622
2021-01-28MLBEDSW-3772 Reshape removalPatrik Gustavsson
-Removed reshapes in the original graph -Removed the addition of reshapes to the optimized graph -Reshapes with different ifm/ofm quantisation will remain Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I94862be53dac0d7434815e2aee5ca678228495f8
2021-01-14MLBEDSW-3654 Fix for split/concat opsPatrik Gustavsson
Fix for split/concat ops - set correct ifm_shapes in pass packing Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I7373b1743e4511b6c1dfaa398b927fbb1b454f60
2020-12-23MLBEDSW-3804 Add missing check for npu_opPatrik Gustavsson
Add missing check for npu_op Op ifm ofm shapes only valid for npu_ops. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I73624c8e122fee510ab8320172b8b3a648a6f070
2020-12-22MLBEDSW-3790 Fix for cpu ops has no op.ifm_shapesPatrik Gustavsson
Fixes for MLBEDSW-3790, MLBEDSW-3792 and MLBEDSW-3794 3790: Fix for cpu ops has no op.ifm_shapes - Check before added to pass 3792: Debug database, fix for cpu op with 5D tensor - Do not try to convert to 4D 3794: Fix covert ResizeBilinear to 2x2 maxpool -set ifm ofm shapes Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I9144dc77e2f6e5c3707c5bf2f204c1d13d5148ba
2020-12-21MLBEDSW-3786 Fix index out of range on ofm_shapesPatrik Gustavsson
Ofm_shapes only set on operator for npu_ops. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Iab98e24132f3a4004debce9013355e2ef16b0b6f
2020-12-21Revert "Revert "MLBEDSW-3645 4D class for op ifm/ofm shapes""patrik.gustavsson
This reverts commit df0a5905177f3a1b836076bc3f9f39b2e86f1794. Reason for revert: <INSERT REASONING HERE> Change-Id: I891c66fb29db9d25e942947e8d1c29a10610de51
2020-12-21Revert "MLBEDSW-3645 4D class for op ifm/ofm shapes"patrik.gustavsson
This reverts commit bf31d647dc5df47410ee577b12427ddf076d816b. Reason for revert: <INSERT REASONING HERE> Change-Id: I7b6c585b7658f94dbaa916c2b6bfe9fb463b8d37
2020-12-21MLBEDSW-3645 4D class for op ifm/ofm shapesPatrik Gustavsson
Add 4D shape class for op Ifm/ofm shapes Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ic0a98da9d2f9d085605e39a9ab5a26bad6e702a3
2020-12-18MLBEDSW-3654 Add/use op ifm/ofm shapesPatrik Gustavsson
Add ifm/ofm shapes to op Changed to rely on these shapes Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I571535a1dcadc2bdb04a3c727a8e1c49703b174d
2020-12-08MLBEDSW-2836 Change sets to tuplesMichael McGeagh
Replace conditional checks against sets with tuples. If not requiring uniqueness, or complex set operations, it is quicker to use tuples instead. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Ie8732c8d46067244963936c53f0ec81adda50372
2020-12-08[MLBEDSW-3690] Refactor SoftmaxFredrik Svedberg
Move operator generation code to common functions. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I02e185fd793a96ae435fa7d235c9d1e97f388a03
2020-11-11MLBEDSW-3019: Add profiling debug databaseTim Hall
- Added mechanism to track input to output graph transforms for debugging the resultant command stream. - Provides base implementation for MLBEDSW-2661 Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I2dfe8a409fbde7ad0282bfab5acb11ba1c8b82d8
2020-10-14Revert "MLBEDSW-3219: Suppress CPU info for Const/Placeholder"patrik.gustavsson
This reverts commit 04986c0016e59993563490fe67052371fc0e1ad2. Reason for revert: Merged by mistake Change-Id: I150ad9ba7074ad1e80f21180aeba56a454d9f748
2020-10-14MLBEDSW-3219: Suppress CPU info for Const/PlaceholderLouis Verhaard
Suppress info print that Const/Placeholder/SubgraphInput are not supported on the NPU. Change-Id: I689d25481df0cd10487484c9f639e4253df081ee Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-09MLBEDSW-3218: Added operator indices Quantize/DequantizeLouis Verhaard
Change-Id: Idcf1665f95ddecc2a12ff0e714f645263981d501 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-08MLBEDSW-3148: Refactor OperationLouis Verhaard
- op.type is now an enum instead of a string - Removed unused operator codes - Refactored some attributes like npu_block_type, fused_activation_function - Refactored operator index calculation - Refactored a number of operator sets Change-Id: I641f65ee375794b7aec42abc0664251ae37d78e8 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-22MLBEDSW-2813: Handle non-const weights and check shapesAndreas Nevalainen
- Added check for non-constant weights in supported operators - Added check ifm & ifm2 shapes - Handle None tensors for CPU operators - Handle missing attributes for Cast operator Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com> Change-Id: I2f16d3d44d0c6da5237550b39273cdb9cc3c7607
2020-09-11MLBEDSW-2745 Support relus with differing scalesMichael McGeagh
In the event we have a relu op with different input and output scales, we need to fuse it with a nop avgpool. Also refactor the existing avgpool nop code to a common function. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Iedf4513e7595ee4ee1777ba0b1eb38a8df8aed5e
2020-08-27MLBEDSW-2786: Fix IFM order in binary operationDiqing Zhong
- Setup ifm/ifm2 based on primary op's inputs Change-Id: I727eab473165d7cc876b70fa8873fbc0c1480fb5 Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2020-08-19MLBEDSW-2728: Only insert primary op for NPU opsJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I04f299e2d3319113fedf2fa401b88bae64fea66d
2020-08-17MLBEDSW-2688: Improved LUT supportLouis Verhaard
- Support for more than one 256-byte LUT in SHRAM - No DMA is performed for a LUT that is already located in SHRAM - Added MemArea.Shram, used for LUT, to avoid false address collision asserts during SRAM tensor allocation - Added read access to LUT in memory access calculation Change-Id: If4d1eded5ed029d253f4f5efb2d80495fc3eac99 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-08-12MLBEDSW-2637 Utilise new tensor and operator funcsMichael McGeagh
add_input_tensor, set_output_tensor, create_const_tensor and create_reshape_tensor have recently been added. This replaces all found existing instances with these new helper functions Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: If33be8dbf237b2087b562b03cdeb51da1f99a786
2020-08-10MLBEDSW-2639: Moved the IFM/IFM2 order switch to register cmd stream generatorJacob Bohlin
For binary elementwise ops with broadcasting in first IFM. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I25af67be8d3a852247989bc3ddc8e08e946f6bfa
2020-08-05[MLBEDSW-2335] SoftMax int16Fredrik Svedberg
Added graph rewrite of Softmax for int16. Change-Id: Id7885af6056a23e8b8362fb61ae94283251eb398 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-07-10MLBEDSW-1497: Add Quantize operator supportJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: Iaf4d7ab9c32b0d783072c5f131a61bfebe77cc16
2020-06-18MLBEDSW-2506: Swap broadcast input if applicableCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: I6e8a97486aa2e1a21101f7cc32cd3024a376162a
2020-06-18MLBEDSW-1828: Ifm/ifm2 order is reversed in some cases of splitCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: Ib8d66f8b3c0467966165c1b53aeb7da7c8764c89
2020-06-18MLBEDSW-1716: Transpose Convolution supportJacob Bohlin
Change-Id: Ie6d8d6de9f3447f19ba06aafa9fa480fc96a973b Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
2020-06-18Add reorder-python-import pre-commit hookDiego Russo
Also updated README.md Change-Id: I118309c61f4d00e8508d6b888c606995490fba39 Signed-off-by: Diego Russo <diego.russo@arm.com>
2020-06-18MLBEDSW-1498: Add Resize_Bilinear operator supportDwight Lidman
This patch adds support for the ResizeBilinear operator. It is implemented using a 2x2 Nearest Neighbor upscale followed by a 2x2 Average Pool. Depending on the argument align_corners the output is either of shape: - (2 * M, 2 * N) when align_corners == True, or - (2 * M - 1, 2 * N - 1) when align_corners == False where (M, N) is the input shape. The padding mode is SAME when align_corners == True and VALID when align_corners == False. The argument half_pixel_centers is out of scope and is as of now ignored. Note that only upscaling by a factor of 2 is supported. Change-Id: Ia6d6d010c4f1bb13f5f839bc8d16872a626d9a3b Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
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