aboutsummaryrefslogtreecommitdiff
path: root/ethosu/vela/operation.py
AgeCommit message (Collapse)Author
2022-04-27MLBEDSW-6425: Update to TensorFlow 2.8Rickard Bolin
Update the flatbuffers generated code to comply with TensorFlow 2.8 Signed-off-by: Rickard Bolin <rickard.bolin@arm.com> Change-Id: Ia65325b88745e49dbafa803a38c0ea0e7d0478ba
2022-04-20MLBEDSW-6371: Output diff caused by operator clone bugRickard Bolin
- Modify the operator clone function to also clone resampling mode attribute. A previous patch changed the ifm resampling mode to be an attribute of an operator rather than a tensor but did not modify the operator clone function to clone the new attribute. Signed-off-by: Rickard Bolin <rickard.bolin@arm.com> Change-Id: I7a2f6103666a0997f657de20ad962e849976b904
2022-03-21MLBEDSW-6298: MLCE: Unable to find a valid block configTim Hall
- Fixed a bug due to ResizeBilinear modifying the attributes of a shared IFM - The ifm_resampling_mode is now an attribute of an operator rather than a tensor - Changed all calls to try_block_config() to use the attribute rather than recalculating it in multiple places Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I4641e9cd6b049bd4186776d98e3e751c5e5bcc06
2022-03-21MLBEDSW-3367 Add mypy to pre-commitJonas Ohlsson
Add mypy to pre-commit and clean up all reported errors. Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com> Change-Id: If7dc869f5fecdb0e2db40f14e7d9db21aa33df71
2022-01-21MLBEDSW-4870: Update to TensorFlow 2.7Rickard Bolin
Update the flatbuffers generated code to comply with TensorFlow 2.7 Signed-off-by: Rickard Bolin <rickard.bolin@arm.com> Change-Id: Iff29b05a6e145245861329b4ff9fc9fbd968da53
2021-10-14MLBEDSW-5162 MLCE: Vela [3.1.0] falling to run with yolov4_int8.tfliteJames Ward
* fix indices for tflite mapping of EXP operator * fix indices for tflite mapping of Transpose operator * ensure read offset after slice is aligned to 16 bytes for NHCWB16 or force linear format * add unit test to ensure mapping of indices is consistent across TFLite, TOSA and NNG Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I17b6e44bc06853325d5eea62a558418ee1ebefe8
2021-10-01TOSA: Add support for Identity operationPatrik Gustavsson
Added support for Identity operation. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: If00b30528932f7531807ce3914d6c1875ab72fa4
2021-09-20TOSA: Elementwise Rank > 4 and Batch > 1Patrik Gustavsson
Added support for elementwise operations: -Support for up to Rank == 6 -Support for Batch > 1 for Rank == 4 -For binary elementwise ops this includes handling of broadcasting in dimensions above H-dimension Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I73850bbfb288077a99bd2ceecbf989172016da24
2021-09-15TOSA: Support for TABLE operator (int8)Patrik Gustavsson
Added support to map TABLE operator to LUT. Limitations: -Only supported for int8 -TABLE input must be constant This also adds the support for TFLite legalisation of Tanh/Sigmoid (int8/uint8). Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I1a95f61fb02fdd42c4a690494418cc0765c8b275
2021-09-09TOSA: Add support for PADPatrik Gustavsson
Added support for TOSA PAD operator in line with legacy support Limitations: -Rank <= 4 -N = 1 if Rank = 4 for ifms/ofm -only padding in W and H dimensions -bool_t not supported Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I511608202b4c9bf6d86285b559c517fb41741fdf
2021-09-03TOSA: Added support for ADD, SUB and MULPatrik Gustavsson
Added support for ADD, SUB and MUL Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I52acdc126b16e2cf4096bcf7a77023ea7d204998
2021-09-03TOSA: Added Depthwise supportPatrik Gustavsson
This is mainly to add support for depthwise conv2d with dephmultiplier = 1. (But there are no testcases suited, all I have sourced has depth_multiplier set to 2, which is not supported.) -Added support for depthwise conv2d. -Added support for removing Transpose of constant data -Added support for removing reshape Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I143e6246becfa78fd9f7510af0bf0d6b3fbbf2c7
2021-08-05MLBEDSW-4854: Update to TensorFlow 2.5Dwight Lidman
This commit updates the flatbuffers generated code to comply with TensorFlow 2.5, as well as stripping away some legacy code. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I01fe47ec2bde6e78fdde21ee1bc0a71f560c53ae
2021-07-09MLBEDSW-4840 Move setting of input indices to tflite readerPatrik Gustavsson
Mapping to internal input indexing has been added to tflite_reader.py and tosa_reader.py. And the other way around in tflite_writer.py. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I4d8596e747cfa7c4203884c4e785eb1977e2bcc1
2021-07-08MLBEDSW-4838 Added basic TOSA support.Patrik Gustavsson
Added basic TOSA support, enabling Vela to read and compile a .tosa file corresponding to CONV2D + Rescale + Clamp, and writing it to an optimized .tflite file. The optimized .tflite file, will in this case, hold a commandstream where the Rescale and Clamp has been fused into the CONV2D. The optimized tflite file is not output from Vela. -Added support to read .tosa file into Vela internal structure. - Added tosa_reader.py, tosa_mapper.py and helper files stored under tosa/ - Support for this limited to ~10 ops -Added reader_util.py for functions common for TOSA and TFLite -Added tosa_graph_optimiser.py -Added support to fuse Rescale into convolution -Modified handling for padding -Added support to fuse Clamp to previous op -Added graph_optimiser_util.py -Moved functions common for TOSA/TFLite graph optimization to this file. -Renamed graph_optimiser.py to tflite_graph_optmiser.py -Added separate tosa_supported_operators.py -Added supported_operator_util.py -For functions in common for TOSA/TFLite Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ic3c540504ec8c5eb4771397fdc6882050ecf33ab
2021-05-27MLBEDSW-4034: New Scheduler Size or Performance OptimisationTim Hall
- Merged dev/scheduler at 83639f90e8c828f70de6e29142355a940224959b Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I0050529d4b42da93768c7264296434dd877fb5b4
2021-03-16MLBEDSW-4223: Full support for PAD operatorLouis Verhaard
- Added full support for PAD operator - Hardware padding is still used whenever possible - Bug fix Pad followed by max pool if IFM contains negative values Change-Id: Ifc64d1943737d94466f5e2821009dab12a49a965 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-02-25MLBEDSW-1499: Add MEAN operatorDwight Lidman
This commit adds support for the MEAN operator, with some caveats. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I165cb26cb5aefd68e70d2cfc68291ccf7b778921
2021-02-17MLBEDSW-4022: support PAD followed by pool operatorLouis Verhaard
PAD followed by max/average pool is run on NPU if NPU padding can be used. Average pool is converted to depthwise. Change-Id: Icc3652e6d9ecff5ac3dc7d92080313d90c245404 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-02-17[MLBEDSW-3813] Fix LSTM operator pass throughFredrik Svedberg
Fixed pass through of LSTM operator. Change-Id: I23140c69ab6cdc83f6bb8129256b4cc6a7c5ffac Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2021-02-11MLBEDSW-3774 Remove SplitSliceReadPatrik Gustavsson
Removed SplitSliceRead from subgraph during graph optimisation. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I9315d4c2a6767828dd2b4e66823d73b10ebee99c
2021-02-08MLBEDSW-3937 Fix check for NHCWB16 for FCPatrik Gustavsson
Fix check for NHCWB16 for modifying FC input. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ie50c32ca079afadd0af9b7b909820794ceee373c
2021-02-05MLBEDSW-3771: Updated to TF 2.4 flatbuffer schemaTim Hall
Updated tflite loader and mappings from tensorflow 2.3 to tensorflow 2.4 Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I55884000ee139baf639bb0377008e0534f72fe94
2021-02-01MLBEDSW-3903: Bug fix PAD operatorLouis Verhaard
- Added checks for unsupported pad sizes in PAD operator - Bug fix right pad/bottom pad calculation when replacing PAD operator by hardware padding Change-Id: Ib84be711277d987052f14352ab386e0e0b774987 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-01-29MLBEDSW-3224: Support HardSwishDiqing Zhong
Change-Id: If49abc31f093f1bd3393bee86f821fd35972086f Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2021-01-29MLBEDSW-3772 Fix FC with changed inp shapePatrik Gustavsson
When FC input is fixed by changing ifm_shape, avoid_NHCWB16 must be set to ifm. -Fixed issue with ResizeBilinear -Changed to post order for concat ops in graph optimisation Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ie0c6a86637c210c0833ae9b2f8e7c494c5d4f66e
2021-01-28MLBEDSW-3772 Reshape removalPatrik Gustavsson
-Removed reshapes in the original graph -Removed the addition of reshapes to the optimized graph -Reshapes with different ifm/ofm quantisation will remain Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I94862be53dac0d7434815e2aee5ca678228495f8
2021-01-20[MLBEDSW-2787] Remove op.attrs["rescale"] in softmax.pyFredrik Svedberg
Added RescaleAdd operation to avoid non-standard attribute "rescale" for Add operation. Also changed ResizeBilinear in the same way. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I1d286f63890585c06b8a161df1ff77e3f844a4b9
2020-12-22MLBEDSW-3499: Support for PAD operatorLouis Verhaard
Replaces the PAD operator by hardware padding when possible. Change-Id: I9dce0885e51a4a73715824d7368637222e39b2b3 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-12-21Revert "Revert "MLBEDSW-3645 4D class for op ifm/ofm shapes""patrik.gustavsson
This reverts commit df0a5905177f3a1b836076bc3f9f39b2e86f1794. Reason for revert: <INSERT REASONING HERE> Change-Id: I891c66fb29db9d25e942947e8d1c29a10610de51
2020-12-21Revert "MLBEDSW-3645 4D class for op ifm/ofm shapes"patrik.gustavsson
This reverts commit bf31d647dc5df47410ee577b12427ddf076d816b. Reason for revert: <INSERT REASONING HERE> Change-Id: I7b6c585b7658f94dbaa916c2b6bfe9fb463b8d37
2020-12-21MLBEDSW-3645 4D class for op ifm/ofm shapesPatrik Gustavsson
Add 4D shape class for op Ifm/ofm shapes Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ic0a98da9d2f9d085605e39a9ab5a26bad6e702a3
2020-12-18MLBEDSW-3654 Add/use op ifm/ofm shapesPatrik Gustavsson
Add ifm/ofm shapes to op Changed to rely on these shapes Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I571535a1dcadc2bdb04a3c727a8e1c49703b174d
2020-12-18vela: Move special error casesMichael McGeagh
Due to an issue with potential cyclical imports, especially when running individual parts of vela standalone for example with pytest, the specialised error functions are moved out of errors.py to their respective locations. The use of getattr over isinstance prevents the need to import the tensor/operator class causing the cyclical import issue. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: If8cee4b1a2562660c6a47e1c7aeb5d7fd4dd1fca
2020-12-17MLBEDSW-3694 Replace padding with enumMichael McGeagh
Use an Enum instead of a bytestring to specify VALID or SAME padding Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: I4e87f8c32b3bfac176d822a68de061e85a558fce
2020-12-14MLBEDSW-3653: Fix type errors in annotated filesDwight Lidman
This commit corrects a number of type errors reported by mypy and refactors some parts of the code which are no longer necessary after making adjustments to satisfy mypy. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I16b880b228e57f2a92fb8936f53e94886e0f9f44
2020-12-08[MLBEDSW-3690] Refactor SoftmaxFredrik Svedberg
Move operator generation code to common functions. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I02e185fd793a96ae435fa7d235c9d1e97f388a03
2020-11-27MLBEDSW-3633: SplitV incorrectly placed on CPUJacob Bohlin
Minor fix in SPLITV tensor indexing for supported operators check. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: If8fa702bfbb25a4a7e5bdb136a19ef72eec7e1c2
2020-11-13MLBEDSW-839: Code generation using external API2.0.0.rc1Louis Verhaard
Added external API to generate register command streams. Existing code generation has been refactored to make use of this API. Change-Id: Ibb4c2b167809869f16470b14da24f08a65c82b7b Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-11-04MLBEDSW-2412 All constraints have been refactoredMichael McGeagh
All existing constraints have now been refactored using the new framework. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Ic9ba0d7040cb9f114b959a949bfdf777f86752c7
2020-10-21vela: Refactor operators to use Kernel objectsTim Hall
- Normalise kernel availability by requiring all operators offer a kernel describing how much data they consume from the source, per OFM element, regardless of whether kernels are relevant to the operation. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Idbcff64879fc2eccf292b6208a7d2038eb388017
2020-10-16MLBEDSW-3004: UnpackReshaped can't be serialisedDwight Lidman
This commit fixes a bug where a rewritten Unpack operator is placed on the CPU and crashes Vela during serialisation due to the type having changed and there not being a mapping for the modified op type. The solution is to move the fixup_unpack_output function to the graph optimisation pass B, allowing the supported op check to run before it. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Ic6bd4c70a478fd61adf377cb487f5b9253130314
2020-10-14Revert "MLBEDSW-3219: Suppress CPU info for Const/Placeholder"patrik.gustavsson
This reverts commit 04986c0016e59993563490fe67052371fc0e1ad2. Reason for revert: Merged by mistake Change-Id: I150ad9ba7074ad1e80f21180aeba56a454d9f748
2020-10-14MLBEDSW-3219: Suppress CPU info for Const/PlaceholderLouis Verhaard
Suppress info print that Const/Placeholder/SubgraphInput are not supported on the NPU. Change-Id: I689d25481df0cd10487484c9f639e4253df081ee Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-09MLBEDSW-3218: Added operator indices Quantize/DequantizeLouis Verhaard
Change-Id: Idcf1665f95ddecc2a12ff0e714f645263981d501 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-08MLBEDSW-3148: Refactor OperationLouis Verhaard
- op.type is now an enum instead of a string - Removed unused operator codes - Refactored some attributes like npu_block_type, fused_activation_function - Refactored operator index calculation - Refactored a number of operator sets Change-Id: I641f65ee375794b7aec42abc0664251ae37d78e8 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-29MLBEDSW-2031: LUT support tanh/sigmoidLouis Verhaard
Uses LUT for int8/uint8 based tanh/sigmoid. Change-Id: Ib6ac5a5c958ab9a17e47f620b22c3e22d8d60321 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-28MLBEDSW-3035: Updated StridedSlice checksLouis Verhaard
Updated supported operator checks for StridedSlice: - allow negative indices in begin/end values - added more checks on shapes Change-Id: I3ac76bfa6b313f0e2250f0749f152fb0e3aa033c Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-11MLBEDSW-2745 Support relus with differing scalesMichael McGeagh
In the event we have a relu op with different input and output scales, we need to fuse it with a nop avgpool. Also refactor the existing avgpool nop code to a common function. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: Iedf4513e7595ee4ee1777ba0b1eb38a8df8aed5e
2020-09-08MLBEDSW-2935: LUT fusing with preceding operatorLouis Verhaard
Allows fusing of LUT with a preceding operator regardless of input/output scale. Change-Id: Ia378adbb3fe61d71299feb085f7313377e0efa39 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
generated by cgit v1.2.1 (git 2.23.0) at 2024-06-26 23:37:04 +0000