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Added basic TOSA support, enabling Vela to
read and compile a .tosa file corresponding to
CONV2D + Rescale + Clamp, and writing it to an
optimized .tflite file.
The optimized .tflite file, will in this case, hold
a commandstream where the Rescale and Clamp has been
fused into the CONV2D.
The optimized tflite file is not output from Vela.
-Added support to read .tosa file into Vela
internal structure.
- Added tosa_reader.py, tosa_mapper.py and
helper files stored under tosa/
- Support for this limited to ~10 ops
-Added reader_util.py for functions common
for TOSA and TFLite
-Added tosa_graph_optimiser.py
-Added support to fuse Rescale into convolution
-Modified handling for padding
-Added support to fuse Clamp to previous op
-Added graph_optimiser_util.py
-Moved functions common for TOSA/TFLite graph
optimization to this file.
-Renamed graph_optimiser.py to tflite_graph_optmiser.py
-Added separate tosa_supported_operators.py
-Added supported_operator_util.py
-For functions in common for TOSA/TFLite
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ic3c540504ec8c5eb4771397fdc6882050ecf33ab
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- Merged dev/scheduler at 83639f90e8c828f70de6e29142355a940224959b
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I0050529d4b42da93768c7264296434dd877fb5b4
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Improved --verbose-graph output by adding labels to each print.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I49039ff6af1c06f49208591f02effa4ff73f982a
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A recent fix to another MEAN bug introduced a new
bug. The bug was due to some incorrect logic for
checking the axis attribute.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I65d3486a12e029f7c4450074f03fcd1974f65d8a
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When the operations are merged some later passes are confused by start
and end coordinates for the convolution not being along the edges of
the IFM, and omitting padding. But we need the zero padding to keep
the output the same as before the transformation.
Also fixes bug where Vela could crash if convolution had explicit
start coordinate.
Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
Change-Id: I8449d237350d528f83738b2f09124f1ed79c07ca
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When a MEAN operator with a single reduction axis
specifies the axis index attribute as an array with
a single element rather than a scalar index, the
operator is placed on the CPU even though it is
technically supported.
This commit fixes this issue and also adds some new
tests for the axis constraints.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Ia287f3b9cc80a805e972cd4b2962e52526a8dc16
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Also applies to unpack.
Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
Change-Id: I07e7083aeb6aefd6e26f9d134b858080f28f1719
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Fixed the check related to if there are any CPU
producers/consumers.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I0ed08c650d1ca34e8e148aee68a5ed09c25fdd87
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Not only the sg input outputs need to be considered
before removing Reshape.
Added check if Reshape ifm/ofm is produced respectively
consumed by CPU. Handling is the same as if tensor is
sg input/output.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: If509e1d23e3f22ed4c963d8dabd8c00c6b9c07e3
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Check if non linear tensor format can be used is
refactored.
-Flag avoid_NHCWB16 replaced with needs_linear_format
-Checking restrictions located to one function in graph optimiser.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Iec5c7996a1a6039cad052197f1ae56f7c0290440
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This is a small commit which changes one of
the four MEAN implementations to a simpler
one, using an AvgPool instead of a
DepthwiseConv.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I9e8af071e8b820796577ee4792b4812a1212602b
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This commit fixes a bug where the OFM zero point
would assume values outside of [0, 255] due to it's
usage as a stand-in for a bias when emulating the
TensorFlow Lite implementation of MEAN.
The solution is to adjust for the bias using an
ADD operator with the bias value as an int16 const
tensor. The 16-bit integer is needed as the bias
is 32 bits in the original implementation but can
effectively assume values in the range [-255, 255].
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I84df48ea89bb559954f1b2c289b65e08a6418274
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This commit adds support for emulating the behavior
of the QuantizedMeanOrSum implementation of MEAN in
TensorFlow Lite.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Ifd24e0e678e2f85cd66ab82deeaaf010d5351b1e
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- Added full support for PAD operator
- Hardware padding is still used whenever possible
- Bug fix Pad followed by max pool if IFM contains negative values
Change-Id: Ifc64d1943737d94466f5e2821009dab12a49a965
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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LeakyReLU IFMs will now have unique addresses
and the alpha tensor will have correct scaling.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: If94fa91a0b61175309ac450bf6b38a63362780ab
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This commit adds support for the MEAN operator,
with some caveats.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I165cb26cb5aefd68e70d2cfc68291ccf7b778921
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PAD followed by max/average pool is run on NPU if NPU
padding can be used. Average pool is converted to depthwise.
Change-Id: Icc3652e6d9ecff5ac3dc7d92080313d90c245404
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Fix avoid cascading for spilling.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: If86189bd1566eaa14387dfc2c02e3324ea6c184e
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Removed SplitSliceRead from subgraph during
graph optimisation.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I9315d4c2a6767828dd2b4e66823d73b10ebee99c
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-Removed ConcatSliceWrite from the optimised graph.
Always executed as avgpool, which is equivalent with
before the patch.
-Added copy op to enable more removal of reshapes.
Sg input/outputs need to remain. When Reshape input and
outut, are sg input/outputs a copy op is needed to
be inserted, in order to remove the reshape.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Id7be9966673ae34499e8518a5544104493fe326b
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Fix check for NHCWB16 for modifying FC input.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ie50c32ca079afadd0af9b7b909820794ceee373c
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- Removed requirement for cloning shapes when unique values required
by forcing top-level immutability. This alleviates issues with Shapes
being unintentionally shared and then mutated as if value-types.
- Shape4D fields can no longer be assigned without replication.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ic0dbfa349eb0215eabefb4f4e2cf99f12d83699c
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Removed fixup_act_reorder from graph optimisation.
As Reshape ops has been removed this optimization
should not be needed.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I2c375ee7787bf15f66c1e16514ed62727934d869
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- Added checks for unsupported pad sizes in PAD operator
- Bug fix right pad/bottom pad calculation when replacing PAD operator
by hardware padding
Change-Id: Ib84be711277d987052f14352ab386e0e0b774987
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Change-Id: If49abc31f093f1bd3393bee86f821fd35972086f
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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When FC input is fixed by changing ifm_shape,
avoid_NHCWB16 must be set to ifm.
-Fixed issue with ResizeBilinear
-Changed to post order for concat ops in graph optimisation
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ie0c6a86637c210c0833ae9b2f8e7c494c5d4f66e
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unfuse_activation_function moved into rewrite_concat_ops
Need to be handled before converting ConcatTFlite to
ConcatSliceWrite.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ieeaed4d28b38de3a8dcacaf708962b9d8161a161
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-Removed reshapes in the original graph
-Removed the addition of reshapes to the
optimized graph
-Reshapes with different ifm/ofm quantisation will remain
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I94862be53dac0d7434815e2aee5ca678228495f8
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Bug fixes for 16-bit leaky relu with different quantizations for IFM/OFM:
- Overflow error occurred for alpha == 0
- The identity multiplication overwrote the result of the alpha
multiplication
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: I18f8d121f6e7c598b721c472b476b9285eeff543
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Added RescaleAdd operation to avoid non-standard attribute
"rescale" for Add operation. Also changed ResizeBilinear
in the same way.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I1d286f63890585c06b8a161df1ff77e3f844a4b9
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Fix for split/concat ops
- set correct ifm_shapes in pass packing
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I7373b1743e4511b6c1dfaa398b927fbb1b454f60
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Added op.set_ifm_ofm_shapes to the convertion functions
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I727d4cf34395bc0997863df1ac89537f84f9c7c8
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Sets IFM's resampling mode for transpose convolutions.
Change-Id: I11744a932aea7c11fa70036c43a7ed01ea4b2929
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Replaces the PAD operator by hardware padding when possible.
Change-Id: I9dce0885e51a4a73715824d7368637222e39b2b3
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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- Reshape/rearrange IFM and weight tensor for better HW utilization
- Update estimator to cover this case
Change-Id: I4be70a69fa600a1951bf1c247f9973e6cc9b03f4
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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Fix converting axis to 4D axis.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I83501494738f402b374efd8a369e5001f17b8152
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Fixes for MLBEDSW-3790, MLBEDSW-3792 and MLBEDSW-3794
3790: Fix for cpu ops has no op.ifm_shapes
- Check before added to pass
3792: Debug database, fix for cpu op with 5D tensor
- Do not try to convert to 4D
3794: Fix covert ResizeBilinear to 2x2 maxpool
-set ifm ofm shapes
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I9144dc77e2f6e5c3707c5bf2f204c1d13d5148ba
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This reverts commit df0a5905177f3a1b836076bc3f9f39b2e86f1794.
Reason for revert: <INSERT REASONING HERE>
Change-Id: I891c66fb29db9d25e942947e8d1c29a10610de51
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This reverts commit bf31d647dc5df47410ee577b12427ddf076d816b.
Reason for revert: <INSERT REASONING HERE>
Change-Id: I7b6c585b7658f94dbaa916c2b6bfe9fb463b8d37
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Add 4D shape class for op Ifm/ofm shapes
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ic0a98da9d2f9d085605e39a9ab5a26bad6e702a3
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Add ifm/ofm shapes to op
Changed to rely on these shapes
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I571535a1dcadc2bdb04a3c727a8e1c49703b174d
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Use an Enum instead of a bytestring to specify VALID or SAME padding
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: I4e87f8c32b3bfac176d822a68de061e85a558fce
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Minor refactoring to use fstrings.
Improve Error classes to correctly inherit the base class.
Use existing exception classes instead of plain exceptions where it
makes sense.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: I0941c04e91010da1db77299517a8e2d896371e77
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- We have combined estimates for conv and fc, add the fix back
Change-Id: I49a29c716189b37b387df4b46efab5f4e6125994
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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Replace conditional checks against sets with tuples.
If not requiring uniqueness, or complex set operations, it is quicker to
use tuples instead.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: Ie8732c8d46067244963936c53f0ec81adda50372
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Move operator generation code to common functions.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I02e185fd793a96ae435fa7d235c9d1e97f388a03
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Do not use DMA for weights of a FullyConnected op that has
been converted to a Conv2D.
Change-Id: Ibf6710c0a1723c8b48c563ca204f274af5ca88ce
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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This reverts commit 15a8e803844b286fe9533e1cf703c76a77b090a8.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I64169443f473c9ba42551281ad6ac4b45856f420
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- Fixed bug due to typo in Op.type refactor
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I55916d90bf792648f496a45c358b7e897c6730ba
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- Improved tensor and scaling query functions
- Fixed bug in convert_batched_fc_to_conv
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ibc3d14036540f27cf5e993beb2163d3e0f5e5933
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