Age | Commit message (Collapse) | Author |
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Vela was not able to parse config file paths entered with forward
slashes. This patch will make it possible to use both forward and
backslashes when specifying paths.
Signed-off-by: Rickard Bolin <rickard.bolin@arm.com>
Change-Id: I0f4cfc16bde5738c73059af6216d2bdc3821c68b
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- Added support to print per operator sram usage and performance
information
- Added new CLI option --verbose-performance to control this feature
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I368599b410e5d441d9804871fc51b7a1049d85b3
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Update version of Black to 22.3.0 due to updated dependencies.
Updates to fix reported issues due to new version.
Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com>
Change-Id: I60056aae452093ce8dcea1f499ecced22b25eef1
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option""
This reverts commit 257a31e93cb2c7a8c06a102211ebb05b3ba78cd8.
Reason for revert: <INSERT REASONING HERE>
Change-Id: If4f565d8c692e2b32903819561591d9e4af619fa
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Relationship to other patches
This reverts commit b6dd9c2e5fcf2885fb42dab567378c8aec22215c.
Reason for revert: <INSERT REASONING HERE>
Change-Id: I50afb5ac4e33e5b8cd4f2aac1f5b94700ab8eeb1
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- Changed mem_type_size() to only return a hard limit
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ia9271c54a592965f88f52fe25a52b3efaca88500
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- Changed Ethos-65 AXI port address width from 48 to 40-bits
- Fixed the use of arena_cache_size in mem_type_size() to cover the
arena as well as the cache memory area
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I826462a0cbd0c061cccbc7c83dde446778a2b1ca
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Refactor supported operators by breaking out model semantics
into its own class. Model semantics checked right after model
read.
Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com>
Change-Id: If442b189efcd91dda01af60b2b3adedfacdf2fad
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Added basic TOSA support, enabling Vela to
read and compile a .tosa file corresponding to
CONV2D + Rescale + Clamp, and writing it to an
optimized .tflite file.
The optimized .tflite file, will in this case, hold
a commandstream where the Rescale and Clamp has been
fused into the CONV2D.
The optimized tflite file is not output from Vela.
-Added support to read .tosa file into Vela
internal structure.
- Added tosa_reader.py, tosa_mapper.py and
helper files stored under tosa/
- Support for this limited to ~10 ops
-Added reader_util.py for functions common
for TOSA and TFLite
-Added tosa_graph_optimiser.py
-Added support to fuse Rescale into convolution
-Modified handling for padding
-Added support to fuse Clamp to previous op
-Added graph_optimiser_util.py
-Moved functions common for TOSA/TFLite graph
optimization to this file.
-Renamed graph_optimiser.py to tflite_graph_optmiser.py
-Added separate tosa_supported_operators.py
-Added supported_operator_util.py
-For functions in common for TOSA/TFLite
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ic3c540504ec8c5eb4771397fdc6882050ecf33ab
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- Merged dev/scheduler at 83639f90e8c828f70de6e29142355a940224959b
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I0050529d4b42da93768c7264296434dd877fb5b4
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This commit resolves a recent regression
in multiple networks (including MobileNet V3).
The regression was caused by a recent change to
IFM block size calculation where a term mistakenly
left out (due to it missing from the spec).
The IFM microblock size has been amended for the
Ethos U-55 128 config and the block size calculations
now use these sizes instead (although equivalent with
OFM microblock sizes).
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Ic504b4becd6c3a26334a7275189d78ff0fe2cf69
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The previous calculation of the IFM block height and width
yielded incorrect block configs when running transpose_conv
networks with certain hardware constraints.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: I8b6936a3e8c37da640bdeac84ecfea8363f910f9
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Added check that configured SRAM size is within bounds.
Change-Id: I5dce3df0788f2b00402e9a541bad11612fa19463
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Added checks during command stream generation to make sure
that address boundaries are respected.
Change-Id: I4dbc693b42d54e35c8fcc785e8be88059e409eec
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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All files which have been updated in 2021 and contain a copyright header have had their headers updated.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: Ia682111a719d16e690433398ccfb69c7e93c1cd1
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Fixed assertion when reading back in an ethos-u custom op.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I275ec9187ffead1e96f2522ecbd658328fa4ef69
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- Fixed bug which stopped DRAM being selected for Ethos-U55
- Fixed type of default values used by burst length and latency
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ic1ae36586e3b4ffe8af8fea1fd23501d434b7731
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Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
Change-Id: I4a5c53d0c5957595fc639b174b2b227ea043d409
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Minor refactoring to use fstrings.
Improve Error classes to correctly inherit the base class.
Use existing exception classes instead of plain exceptions where it
makes sense.
Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com>
Change-Id: I0941c04e91010da1db77299517a8e2d896371e77
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Moved blockdep calculation and other helper functions for
code generation to a separate file.
Change-Id: I2f8ccea478654272ebf42217fc5c1800e9ad177a
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Default arch instances are cached as they are expensive to create,
and they are created often when using the external APIs.
Change-Id: I16802fa767e6750da4227c6266d7c4453c047001
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Blockdep calculation can now handle different sized IFM/OFM.
Change-Id: I898a3c1c3a6778916802f3dbfa658328e5093096
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Added external API to add driver actions to a command stream.
Change-Id: Ie4779c1c745defc5769fa694358470cd6aea191c
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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All external APIs are now exposed by api.py.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: I33f480e424692ac30e9c7d791f583199f31164a7
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- Added sample vela.ini config file
- Changed vela config format, split into system config and memory mode
- Removed unused CPU cycle performance estimation
- Added new CLI options for --memory-mode and --verbose-config
- Changed CLI option --config to take multiple files
- Removed CLI option --global-memory-clock-scales
- Changed error helper functions to raise a VelaError exception
- Refactored to create a new is_spilling_enabled function
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I27c41577e37a3859edb9524cd99784be10ef0a0d
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- Also changed to use Ethos-U where appropriate
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ie45ba2bb3935b305abe897b78b498681296cb7c1
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Usage of shape[-2] could cause index out of range.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: I1b64b117f8236ce9ba321ca03bdb25e5a03a6589
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Added external API to generate register command streams.
Existing code generation has been refactored to make
use of this API.
Change-Id: Ibb4c2b167809869f16470b14da24f08a65c82b7b
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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- Normalise kernel availability by requiring all operators offer a kernel
describing how much data they consume from the source, per OFM element,
regardless of whether kernels are relevant to the operation.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Idbcff64879fc2eccf292b6208a7d2038eb388017
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Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
Change-Id: I9f3671041c2b1497519cf42b5f52e3cd01d9c10a
(cherry picked from commit e8c989f5236cce12d07a6644329935dbbf0ee8e6)
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- op.type is now an enum instead of a string
- Removed unused operator codes
- Refactored some attributes like npu_block_type, fused_activation_function
- Refactored operator index calculation
- Refactored a number of operator sets
Change-Id: I641f65ee375794b7aec42abc0664251ae37d78e8
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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Removed CLI-option permanent-storage
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I03e03205a183bd538292a73a07b095546fa3d95a
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Added checks for not using NHCWB16 for reduce_sum int32 which makes
int8/uint8 softmax work.
Also enabled softmax graph rewrite by default and fixed a saturation
problem.
Change-Id: Ic01bd9ece7e5c3edb2900b7915cc747efe9e5760
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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Added --weight-estimation-scaling, which enables
additional scaling of weight compression scale estimate.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Idcda41257f44901d3a3f345341e07fb1ae8585a9
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Added graph rewrite of Softmax for uint8/int8.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: Iecdd5d2cd3156a601b3313debba4a3562e6be5d7
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- This commit removes unnecessary dependency checks and implements
on-demand calculation of the NPU/DMA dependencies.
Signed-off-by: <tim.hall@arm.com>
Change-Id: I85e681d1ab133bd88f64296dc00500f3c188e777
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- Support for more than one 256-byte LUT in SHRAM
- No DMA is performed for a LUT that is already located in SHRAM
- Added MemArea.Shram, used for LUT, to avoid false address collision
asserts during SRAM tensor allocation
- Added read access to LUT in memory access calculation
Change-Id: If4d1eded5ed029d253f4f5efb2d80495fc3eac99
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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This commit adds a missing entry for TensorPurpose.Unknown,
mapping to MemType.Unknown in the tensor_storage_mem_type
dictionary in the ArchitectureFeatures class in
architecture_features.py
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I6c3d942e8c6f1c71c6496bdd621ca8d46ea76147
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Added graph rewrite of Softmax for int16.
Change-Id: Id7885af6056a23e8b8362fb61ae94283251eb398
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
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*lint
*added unit tests
*added typecheck
*added docstring for the api
Change-Id: Ibd4bc40d4381ac40ad2ea3d500b26c4ec565ab07
Signed-off-by: Manupa Karunaratne <manupa.karunaratne@arm.com>
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Added support for one more memory configuration-
Change-Id: Iac19992386e3e9b80bd519acb1b0a399c47d736f
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
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- Parallelism mode register was being written for non Yoda targets.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I31b50031dab4d615733c4c3790dec8934117f275
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Restrict settings of permanent storage.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Iaa81ee05e8e567b2737825be634baa9085192f0e
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Additional supported memory configurations:
-Permanent_storage = DRAM
-Tensor arena either in DRAM or SRAM
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I20beb7151e306bfdba540e7c0b2a7b478b4d94e1
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Added more accelerator configs.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I77a5ece0b9ed1eddb9b8aa9bb7656a022df95fd6
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- No functional change
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I5ab1198b9d092cd041fa9b85b2dee9900d299bfc
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- Removed --inter-pass-cycle-delay
- Removed --dram-bandwidth
- Removed --batch-size
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ib613f47a9e911c652e522b5aa9ec58ae5391b0fd
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- Add support for marking the tensor purpose of CPU only ops such as LESS which mark their input based upon their output
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ia7898089f0b18ccd4f183e2ef961a67f4d169e4c
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This commit ensures the IFM block size calculation
in architecture_features.py matches the specification
by correctly setting the ifm upscaling factor based on
the upscaling mode.
This requires adding an attribute to the Tensor object
which stores the upscaling mode for that specific
tensor and making sure that information is correctly
carried over to shared_buffer_allocation.py.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I4ab56086f4c694d3bf759bbad30cdb969b4a26db
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Added custom exceptions to handle different types of input errors.
Also performed minor formatting changes using flake8/black.
Change-Id: Ie5b05361507d5e569aff045757aec0a4a755ae98
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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