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2022-05-17MLBEDSW-6271: MLCE: Layer wise Utilization info from VelaTim Hall
- Added support to print per operator sram usage and performance information - Added new CLI option --verbose-performance to control this feature Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I368599b410e5d441d9804871fc51b7a1049d85b3
2022-03-30Update version of Black to 22.3.0Jonas Ohlsson
Update version of Black to 22.3.0 due to updated dependencies. Updates to fix reported issues due to new version. Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com> Change-Id: I60056aae452093ce8dcea1f499ecced22b25eef1
2021-08-19Revert "Revert "MLBEDSW-5028: SRAM target exceeded for legacy_sram_size test ↵patrik.gustavsson
option"" This reverts commit 257a31e93cb2c7a8c06a102211ebb05b3ba78cd8. Reason for revert: <INSERT REASONING HERE> Change-Id: If4f565d8c692e2b32903819561591d9e4af619fa
2021-08-19Revert "MLBEDSW-5028: SRAM target exceeded for legacy_sram_size test option"patrik.gustavsson
Relationship to other patches This reverts commit b6dd9c2e5fcf2885fb42dab567378c8aec22215c. Reason for revert: <INSERT REASONING HERE> Change-Id: I50afb5ac4e33e5b8cd4f2aac1f5b94700ab8eeb1
2021-08-19MLBEDSW-5028: SRAM target exceeded for legacy_sram_size test optionTim Hall
- Changed mem_type_size() to only return a hard limit Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ia9271c54a592965f88f52fe25a52b3efaca88500
2021-08-11vela: Fix Ethos-U65 maximum address rangeTim Hall
- Changed Ethos-65 AXI port address width from 48 to 40-bits - Fixed the use of arena_cache_size in mem_type_size() to cover the arena as well as the cache memory area Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I826462a0cbd0c061cccbc7c83dde446778a2b1ca
2021-07-27MLBEDSW-4853: Refactor supported operatorsJonas Ohlsson
Refactor supported operators by breaking out model semantics into its own class. Model semantics checked right after model read. Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com> Change-Id: If442b189efcd91dda01af60b2b3adedfacdf2fad
2021-07-08MLBEDSW-4838 Added basic TOSA support.Patrik Gustavsson
Added basic TOSA support, enabling Vela to read and compile a .tosa file corresponding to CONV2D + Rescale + Clamp, and writing it to an optimized .tflite file. The optimized .tflite file, will in this case, hold a commandstream where the Rescale and Clamp has been fused into the CONV2D. The optimized tflite file is not output from Vela. -Added support to read .tosa file into Vela internal structure. - Added tosa_reader.py, tosa_mapper.py and helper files stored under tosa/ - Support for this limited to ~10 ops -Added reader_util.py for functions common for TOSA and TFLite -Added tosa_graph_optimiser.py -Added support to fuse Rescale into convolution -Modified handling for padding -Added support to fuse Clamp to previous op -Added graph_optimiser_util.py -Moved functions common for TOSA/TFLite graph optimization to this file. -Renamed graph_optimiser.py to tflite_graph_optmiser.py -Added separate tosa_supported_operators.py -Added supported_operator_util.py -For functions in common for TOSA/TFLite Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ic3c540504ec8c5eb4771397fdc6882050ecf33ab
2021-05-27MLBEDSW-4034: New Scheduler Size or Performance OptimisationTim Hall
- Merged dev/scheduler at 83639f90e8c828f70de6e29142355a940224959b Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I0050529d4b42da93768c7264296434dd877fb5b4
2021-04-21MLBEDSW-4413: MobileNet V3 regressionDwight Lidman
This commit resolves a recent regression in multiple networks (including MobileNet V3). The regression was caused by a recent change to IFM block size calculation where a term mistakenly left out (due to it missing from the spec). The IFM microblock size has been amended for the Ethos U-55 128 config and the block size calculations now use these sizes instead (although equivalent with OFM microblock sizes). Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Ic504b4becd6c3a26334a7275189d78ff0fe2cf69
2021-04-14MLBEDSW-4103: Block config calc updateerik.andersson@arm.com
The previous calculation of the IFM block height and width yielded incorrect block configs when running transpose_conv networks with certain hardware constraints. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: I8b6936a3e8c37da640bdeac84ecfea8363f910f9
2021-03-31MLBEDSW-3461: Check configuration SRAM sizeLouis Verhaard
Added check that configured SRAM size is within bounds. Change-Id: I5dce3df0788f2b00402e9a541bad11612fa19463 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-03-22MLBEDSW-3502: Add address checksLouis Verhaard
Added checks during command stream generation to make sure that address boundaries are respected. Change-Id: I4dbc693b42d54e35c8fcc785e8be88059e409eec Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-02-25MLBEDSW-4064: Update copyright headerserik.andersson@arm.com
All files which have been updated in 2021 and contain a copyright header have had their headers updated. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: Ia682111a719d16e690433398ccfb69c7e93c1cd1
2021-01-28[MLBEDSW-3891] Fix reading back in an ethos-u custom opFredrik Svedberg
Fixed assertion when reading back in an ethos-u custom op. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I275ec9187ffead1e96f2522ecbd658328fa4ef69
2020-12-22MLBEDSW-3763: Vela memory settingTim Hall
- Fixed bug which stopped DRAM being selected for Ethos-U55 - Fixed type of default values used by burst length and latency Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ic1ae36586e3b4ffe8af8fea1fd23501d434b7731
2020-12-16MLBEDSW-3465: Add memory settings into sys configDiqing Zhong
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com> Change-Id: I4a5c53d0c5957595fc639b174b2b227ea043d409
2020-12-14MLBEDSW-2066 Improve Exception messagesMichael McGeagh
Minor refactoring to use fstrings. Improve Error classes to correctly inherit the base class. Use existing exception classes instead of plain exceptions where it makes sense. Signed-off-by: Michael McGeagh <michael.mcgeagh@arm.com> Change-Id: I0941c04e91010da1db77299517a8e2d896371e77
2020-12-07MLBEDSW-3643: Refactor blockdep calculationLouis Verhaard
Moved blockdep calculation and other helper functions for code generation to a separate file. Change-Id: I2f8ccea478654272ebf42217fc5c1800e9ad177a Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-11-27MLBEDSW-3424 Arch cacheLouis Verhaard
Default arch instances are cached as they are expensive to create, and they are created often when using the external APIs. Change-Id: I16802fa767e6750da4227c6266d7c4453c047001 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-11-26MLBEDSW-3562: Improve blockdep calculationLouis Verhaard
Blockdep calculation can now handle different sized IFM/OFM. Change-Id: I898a3c1c3a6778916802f3dbfa658328e5093096 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-11-23MLBEDSW-3425: Added external API for driver actionsLouis Verhaard
Added external API to add driver actions to a command stream. Change-Id: Ie4779c1c745defc5769fa694358470cd6aea191c Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-11-23MLBEDSW-3424: Expose API through separate fileLouis Verhaard
All external APIs are now exposed by api.py. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: I33f480e424692ac30e9c7d791f583199f31164a7
2020-11-20MLBEDSW-3249: Vela config file examplesTim Hall
- Added sample vela.ini config file - Changed vela config format, split into system config and memory mode - Removed unused CPU cycle performance estimation - Added new CLI options for --memory-mode and --verbose-config - Changed CLI option --config to take multiple files - Removed CLI option --global-memory-clock-scales - Changed error helper functions to raise a VelaError exception - Refactored to create a new is_spilling_enabled function Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I27c41577e37a3859edb9524cd99784be10ef0a0d
2020-11-20vela: Rename Yoda to Ethos-U65Tim Hall
- Also changed to use Ethos-U where appropriate Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ie45ba2bb3935b305abe897b78b498681296cb7c1
2020-11-17MLBEDSW-3491: Fix index out of range in code genLouis Verhaard
Usage of shape[-2] could cause index out of range. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: I1b64b117f8236ce9ba321ca03bdb25e5a03a6589
2020-11-13MLBEDSW-839: Code generation using external API2.0.0.rc1Louis Verhaard
Added external API to generate register command streams. Existing code generation has been refactored to make use of this API. Change-Id: Ibb4c2b167809869f16470b14da24f08a65c82b7b Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-10-21vela: Refactor operators to use Kernel objectsTim Hall
- Normalise kernel availability by requiring all operators offer a kernel describing how much data they consume from the source, per OFM element, regardless of whether kernels are relevant to the operation. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Idbcff64879fc2eccf292b6208a7d2038eb388017
2020-10-21MLBEDSW-603: Improve cycle estimation in elementwise opsDiqing Zhong
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com> Change-Id: I9f3671041c2b1497519cf42b5f52e3cd01d9c10a (cherry picked from commit e8c989f5236cce12d07a6644329935dbbf0ee8e6)
2020-10-08MLBEDSW-3148: Refactor OperationLouis Verhaard
- op.type is now an enum instead of a string - Removed unused operator codes - Refactored some attributes like npu_block_type, fused_activation_function - Refactored operator index calculation - Refactored a number of operator sets Change-Id: I641f65ee375794b7aec42abc0664251ae37d78e8 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-09-04MLBEDSW-2819 Removed CLI-option permanent-storagePatrik Gustavsson
Removed CLI-option permanent-storage Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I03e03205a183bd538292a73a07b095546fa3d95a
2020-08-27[MLBEDSW-2846] Do not use NHCWB16 for reduce_sum int32Fredrik Svedberg
Added checks for not using NHCWB16 for reduce_sum int32 which makes int8/uint8 softmax work. Also enabled softmax graph rewrite by default and fixed a saturation problem. Change-Id: Ic01bd9ece7e5c3edb2900b7915cc747efe9e5760 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-08-26MLBED-2822 Added CLI-opt for weight size est.Patrik Gustavsson
Added --weight-estimation-scaling, which enables additional scaling of weight compression scale estimate. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Idcda41257f44901d3a3f345341e07fb1ae8585a9
2020-08-19[MLBEDSW-2657] Softmax uint8/int8Fredrik Svedberg
Added graph rewrite of Softmax for uint8/int8. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: Iecdd5d2cd3156a601b3313debba4a3562e6be5d7
2020-08-18Vela: Rework NPU/DMA dependency insertion (for MLBEDSW-2620)Tim Hall
- This commit removes unnecessary dependency checks and implements on-demand calculation of the NPU/DMA dependencies. Signed-off-by: <tim.hall@arm.com> Change-Id: I85e681d1ab133bd88f64296dc00500f3c188e777
2020-08-17MLBEDSW-2688: Improved LUT supportLouis Verhaard
- Support for more than one 256-byte LUT in SHRAM - No DMA is performed for a LUT that is already located in SHRAM - Added MemArea.Shram, used for LUT, to avoid false address collision asserts during SRAM tensor allocation - Added read access to LUT in memory access calculation Change-Id: If4d1eded5ed029d253f4f5efb2d80495fc3eac99 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-08-12MLBEDSW-2726: Vela crashes when marking tensor with TensorPurpose.UnknownDwight Lidman
This commit adds a missing entry for TensorPurpose.Unknown, mapping to MemType.Unknown in the tensor_storage_mem_type dictionary in the ArchitectureFeatures class in architecture_features.py Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I6c3d942e8c6f1c71c6496bdd621ca8d46ea76147
2020-08-05[MLBEDSW-2335] SoftMax int16Fredrik Svedberg
Added graph rewrite of Softmax for int16. Change-Id: Id7885af6056a23e8b8362fb61ae94283251eb398 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-07-27[EXTAPI] refactor weight compression to be used by an external consumerManupa Karunaratne
*lint *added unit tests *added typecheck *added docstring for the api Change-Id: Ibd4bc40d4381ac40ad2ea3d500b26c4ec565ab07 Signed-off-by: Manupa Karunaratne <manupa.karunaratne@arm.com>
2020-07-07MLBEDSW-2551 Add support for more mem-cfgsPatrik Gustavsson
Added support for one more memory configuration- Change-Id: Iac19992386e3e9b80bd519acb1b0a399c47d736f Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
2020-07-06MLBEDSW-2600: Fix writing of register for wrong architectureTim Hall
- Parallelism mode register was being written for non Yoda targets. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I31b50031dab4d615733c4c3790dec8934117f275
2020-06-30MLBEDSW-2564 Restrict settings of perm. storagePatrik Gustavsson
Restrict settings of permanent storage. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Iaa81ee05e8e567b2737825be634baa9085192f0e
2020-06-25MLBEDSW-2306 Added more supported mem-cfgsPatrik Gustavsson
Additional supported memory configurations: -Permanent_storage = DRAM -Tensor arena either in DRAM or SRAM Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I20beb7151e306bfdba540e7c0b2a7b478b4d94e1
2020-06-23MLBEDSW-2547 Add accelerator_configsPatrik Gustavsson
Added more accelerator configs. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I77a5ece0b9ed1eddb9b8aa9bb7656a022df95fd6
2020-06-18Code clean-up using black and flake8Tim Hall
- No functional change Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I5ab1198b9d092cd041fa9b85b2dee9900d299bfc
2020-06-18MLBEDSW-2471: Remove unused CLI optionsTim Hall
- Removed --inter-pass-cycle-delay - Removed --dram-bandwidth - Removed --batch-size Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ib613f47a9e911c652e522b5aa9ec58ae5391b0fd
2020-06-18vela: Fix tensor purpose for some CPU only opsTim Hall
- Add support for marking the tensor purpose of CPU only ops such as LESS which mark their input based upon their output Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ia7898089f0b18ccd4f183e2ef961a67f4d169e4c
2020-06-18MLBEDSW-1971: Verify ifm block size calculation against specificationDwight Lidman
This commit ensures the IFM block size calculation in architecture_features.py matches the specification by correctly setting the ifm upscaling factor based on the upscaling mode. This requires adding an attribute to the Tensor object which stores the upscaling mode for that specific tensor and making sure that information is correctly carried over to shared_buffer_allocation.py. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I4ab56086f4c694d3bf759bbad30cdb969b4a26db
2020-06-18MLBEDSW-2067: added custom exceptionsLouis Verhaard
Added custom exceptions to handle different types of input errors. Also performed minor formatting changes using flake8/black. Change-Id: Ie5b05361507d5e569aff045757aec0a4a755ae98 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-06-18MLBEDSW-1540: bug fix SHRAM buffer size calculationLouis Verhaard
Updated the algorithm for SHRAM buffer size calculation with block depth alignment. Change-Id: Ie8b10725bb9f52ba4a353b5a2170653833e6e5c0 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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