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2022-01-18Optimize tensor allocation verificationJohan Alfvén
By not comparing items that have already been compared with each other, the number of iterations for the loop is reduced. For large network with long live ranges, this improves compile time significantly. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: I298cd6f109527fc32f6db77ffffca9e765a84ce0
2022-01-12MLBEDSW-5534: Enet_640_640_int8 output diffRickard Bolin
The output diff is caused by not including the kernel dilation when calculating the bottom padding to be used on the last h_stripe. This only shows up when using dedicated_sram since shared_sram does not split into multiple h_stripes and thus uses the padding specified by the skirt instead. Signed-off-by: Rickard Bolin <rickard.bolin@arm.com> Change-Id: I7f643748b153004d65be2124c0ac6c9d21cd803f
2022-01-04Set product in driver action config structJonny Svärd
Signed-off-by: Jonny Svärd <jonny.svaerd@arm.com> Change-Id: Ib398024c2f41beb4f93f7976c678a9fd54af94a5
2021-12-23MLBEDSW-4704: Crash when loading empty constant tensorserik.andersson@arm.com
Fixed a crash caused by loading a network containing operators with empty constant tensors. This could occur when a branched network is split before said branches have converged. We now put the affected operator on the CPU. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: I63e9cd13cecf86d976c5750c727e218c334c32b5
2021-12-20MLBEDSW-5740: Fix assert when setting address on identical LUT tensorsJohan Alfvén
When an LUT tensor address is updated with another existing LUT tensor address, also make sure to update the equivalence id. Signed-off-by: Johan Alfven <johan.alfven@arm.com> Change-Id: I5ce8c608d9ff6d31e16212b1a725b4147dd3f6f1
2021-12-20MLBEDSW-5844: Inconsistent calculation of read shapesTim Hall
- This bug causes a regression in the use of unpack and split operators - The bug is due to the read_shapes attribute being an absolute calculation for slice and strided_slice, but a relative one for unpack and split - The fix is to consistently treat the attribute as a shape relative to the read_offset Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I4504b161be507ea22ca6ee40fbe7808bfe049405
2021-12-17MLBEDSW-5834: split shape is None when split offset is notTim Hall
- This bug causes an exception to occur when trying to index split shape in Box.transform_with_strides_and_skirt() - The bug was due to the read shapes not being initialised when creating a primary op in pass packing Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I3ebd7fc4c7ef5c06488a36d8340a17ae6afd4609
2021-12-17MLBEDSW-4261: External contributions to MLPlatformerik.andersson@arm.com
Added the section "Bug Resolution", which links the user to BUGS.md. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: I36cd5f1317bf050ee91abf33df70dae627e83175
2021-12-16MLBEDSW-5629: MLCE: Model falling when creating explicit_paddingTim Hall
- Issue was due to a previous patch to fix MLBEDSW-4350 - Manually reverted that fix 5fabfcaa2b636b02899b4d6e0ccf95d853986475 - Made a new fix for MLBEDSW-4350 that calculates the padding and skirt by taking into account the split read offsets and shapes Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I96010c1b977011aecbc411a3c91ab3e61af22db4
2021-12-16MLBEDSW-5554: Place MEAN op exceeding max height with axis==1 on CPURickard Bolin
Signed-off-by: Rickard Bolin <rickard.bolin@arm.com> Change-Id: I87dc5963972a7ef91db467b2ff8e0261e9899372
2021-12-02MLBEDSW-5717 Fix for sigmoid int16Patrik Gustavsson
Fixed issue with sigmoid int16 with 1/2048 scaling. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I32718757e3776e6be89fe94a9b38368c78f0006b
2021-11-26MLBEDSW-5417: Update release notes & supported ops3.2.0.rc33.2.0Dwight Lidman
This commit updates the release notes for Vela version 3.2.0. It also updates the SUPPORTED_OPS.md file with new constraints. Updated the API version as a result of the bug fix commit 399c4a2d77df791e5d988c51d7fb1824ac4f266f. Updated Vela version in setup.py. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I181e89f639a1da6013e8511ebe2d7e4f81242916
2021-11-26MLBEDSW-5514: Update PERFORMANCE.mdDwight Lidman
This commit corrects some errors and clarifies the section on cycle counts. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: If1198cb797ffdb2bd23b4a9624cf480a30aacaf6
2021-11-26MLBEDSW-4996: Community bug reporting on ML Platformerik.andersson@arm.com
Created "BUGS.md" which details to the Vela Community how to issue bug report using the Maniphest Bug Tracker. Also added a reference to it in "README.md". Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: I0120a890c8447907e32de6b10a24eceade09df7d
2021-11-25MLBEDSW-5507: Fix vela summary for passesTim Hall
- Removed the passes information as this was no longer correct or useful - Fixed the reporting of the number of CPU operators Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I80bf3f023de7d470af9aa5c6fe7bcb58c60ccd0b
2021-11-25MLBEDSW-3602: Output mismatch on some mobilenet_v1 int8 and int16Tim Hall
- The failing tests contain operations with dynamic tensors which are not supported and therefore they should be placed on the CPU. However, a bug in the removal of RESHAPEs which contain a dynamic shape prevented this happening. - This change adds a check to make sure that RESHAPE ops with a dynamic shape tensor are not removed and instead are placed on the CPU. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I2d7481f7f80f99a0f01df100d956933777e6875a
2021-11-22MLBEDSW-5148: Add author_email to setup.pyDwight Lidman
This commit adds the author_email field with email address <mlg-vela@arm.com> to the setuptools.setup() function in setup.py. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: If3b2605ea9b05a8a4c6f899d8af77cbaec9ce9b5
2021-11-15TOSA: Add ifm ofm elem size into raw output3.2.0.rc2Diqing Zhong
Change-Id: I645496536a6bddf2bd289a87be9d7cef11693954 Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2021-11-12MLBEDSW-5383 npu_find_block_configs() differs between v2.1.1 and v3.1.03.2.0.rc1James Ward
* 1D optimised block_config was incorrectly beign set to the ArchitectureBlockConfig in try_block_config() * Write external API test for the reduced block height case (on H256) Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I9ced7eb31b23730e4423aabbaf769bc72fac8fc9
2021-11-12MLBEDSW-5496: Revert patch for MLBEDSW-4704Dwight Lidman
This reverts commit 0af0d383925968626a7c37, which caused a regression by rejecting previously passing tests as faulty. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: If11737713b6873a67162387e407eadf174b434ec
2021-11-11MLBEDSW-5410 Clarify "Subgraph IO Summary" outputJames Ward
* Add small aesthetic changes to summary * Move "_cpu" suffix from cloned tensor to original tensor such that suffix is no longer externally visible Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I97427561bd9acb04765ae9de6278760511278118
2021-11-05MLBEDSW-5209 Vela: output diff depthwise with non-zero zero pointsFredrik Svedberg
Fixed by adjusting zero points for ops with int8 IFM and asymmetric weights since the reference does not support asymmetric weights for int8 IFM and ignores the zero points. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I2a206a01a471a53aa864a6a3616aa23d2a5a23c8
2021-11-02MLBEDSW-5437: MLCE: Vela ignores back2back Activations in modelTim Hall
- Back-to-back 16-bit activation ops were packed into the same pass because there was no check to disallow it - The solution is to set the appropriate incompatible-flags Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Idb3c741a7b52e0d81c1f687f6ecf78352b7872dd
2021-10-29MLBEDSW-4925: Fix resize bilinear attribute checkerik.andersson@arm.com
Previously we did not check if half_pixel_centers was set. Since we do not support it, these cases should not run on the NPU. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: I9d2675f760424d5cfb67e5d581dd1861ad165b85
2021-10-28MLBEDSW-4704: Vela crashes when serializing subset of Inception v3 networkAlex Matthews
* Add check for tensor with no operations, raising error if its constant-data buffer is empty Signed-off-by: Alex Matthews <alex.matthews@arm.com> Change-Id: Ib210dcc9733e4ecedbada0f430e8b3c4a8384999 Signed-off-by: James Ward <james.ward@arm.com>
2021-10-28MLBEDSW-5440 MLCE: Vela crashing due to mismatch in padding shape in OFMJames Ward
Change convert_pad optimiser to use op.ifm_shapes attribute in place of the fickle op.ifm.shape (which in this case had changed due to the optimised-out reshape) Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I13fbd846ac8d3342afd7844d1041cfa15aaae124
2021-10-27MLBEDSW-5450 MLCE: Vela to handle skip TensorFredrik Svedberg
Added checks to avoid merging elementwise op live ranges for subgraph inputs and outputs, which sometimes caused problems when parts of the network run on CPU. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: Id07ab277a205b8550d19a276559f8904b9a4b4be
2021-10-14MLBEDSW-5184 Unsupported memory only operators on CPUFredrik Svedberg
Make sure unsupported memory only operations are issued to the CPU. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: Ifdf7c3056ab45d707db5b67113549a73133b69c8
2021-10-14MLBEDSW-5396 Vela print_graph_with_tensors crash for optional tensorFredrik Svedberg
Fixed crash in nn_graph.print_graph_with_tensors() and nn_graph.print_graph_with_tensor_quantization() for optional input tensors. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I7a2d23892558006485c5c84842d65aa221dba44b
2021-10-14MLBEDSW-5361 - Fix per-axis quantization supportDwight Lidman
This commit fixes a number of bugs where per-axis quantization would make Vela crash and would not be properly recognized. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I50a461d200274b43ec76f3a7357bf66db6d49964
2021-10-14MLBEDSW-5162 MLCE: Vela [3.1.0] falling to run with yolov4_int8.tfliteJames Ward
* fix indices for tflite mapping of EXP operator * fix indices for tflite mapping of Transpose operator * ensure read offset after slice is aligned to 16 bytes for NHCWB16 or force linear format * add unit test to ensure mapping of indices is consistent across TFLite, TOSA and NNG Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I17b6e44bc06853325d5eea62a558418ee1ebefe8
2021-10-13MLBEDSW-5315 MLCE: Vela to handle skip TensorFredrik Svedberg
Removed graph optimizations no longer needed that caused problems with FullyConnected operators running on CPU being consumed by elementwise operators in Vela. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: Ic7e66141ccd5e9aa8f0022c5ab9e7fd1ba3f6786
2021-10-13MLBEDSW-5369: Fix crash for multiple CPU subgraphsDwight Lidman
This commit fixes an issue where networks with multiple CPU-placed subgraphs would crash due to the assumption that the second subgraph is always placed on NPU. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Ib7e7a9e89d3b0f3a597cf80446f5eb8b132883a4
2021-10-12MLBEDSW-5366 - TLCT: Some TensorTypes were missingDwight Lidman
This commit add some TensorTypes that were missing to the TensorFlow Lite mapping. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I15e80769491e8f3093c14270cf2e312f1568dfc8
2021-10-12MLBEDSW-5284 - MLCE: MEAN batch size constraintDwight Lidman
Adds a constraint on batch size for the MEAN operator. Due to the restrictions imposed by the NHCWB16 format, some operators do not allow batch sizes larger than 1. The MEAN operator uses the operators in its implementation, but the constraint was missing and thus the operator was being wrongly placed on the NPU. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I95e07a9151a6a131c337caa3114da1154be39e49
2021-10-08TOSA: Added support for Const outputPatrik Gustavsson
Added support for a Const operator generating network output. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ia81990a94cc497a58535914124a29e7dbb511247
2021-10-07MLBEDSW-4081 Output diff for some combinations of avgpool + relu (update)Fredrik Svedberg
Fixed regression when the AveragePool has explicit rescaling. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I121a0cbf9ab15c8862739266e088b5db7805446b
2021-10-06MLBEDSW-4081 Output diff for some combinations of avgpool + reluFredrik Svedberg
Fixed zero point issue for AveragePool with fused RELU activation. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I1810752d4575b12ec3dcb67637dc505a62ac5607
2021-10-06TOSA: Update to new schemaPatrik Gustavsson
Update based on schema corresponding to TOSA conformance tests release v0.5. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I517cd5d86ddb3ed8c0f377b4462466387dc3af44
2021-10-06TOSA: Added decomposition of PADPatrik Gustavsson
Added support for: -Rank > 4 and batch > 1 -Tensor dimensions exceeding NPU limit -Padding in any dimension (Implementation for functional compliance, not considering performance) Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ief58fb3233d885f10ba5e68c5374b190efbe9351
2021-10-01MLBEDSW-5286 - MLCE: IndexError for ADD + TANH networkDwight Lidman
Resolves a bug where an IndexError would occur if the same tensor was assigned to both IFM and IFM2 of a binary elementwise operator due to duplicates being allowed in operator inputs but not in pass inputs. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I39a6206a6252f6a848be9f9d4c5a8dc749c71699
2021-10-01TOSA: Add support for Identity operationPatrik Gustavsson
Added support for Identity operation. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: If00b30528932f7531807ce3914d6c1875ab72fa4
2021-10-01MLBEDSW-5013 Output diff for u55-bring-up tests, int16Fredrik Svedberg
Fixed output diff for some architectures due to incorrect IFM buffer size calculation when using NearestNeighbour upscaling. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I0d6d1efc606603cdd6188ae282e7f6babfd7e24e
2021-09-29TOSA: Added decomposition of RESHAPEPatrik Gustavsson
-Added support for unlimited number of dimensions -Added support for tensors exceeding maxlimit of NPU -Fixed regression for PAD Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ib2ce50a30cc5cf396032d85d57dab9968e3fc06a
2021-09-28TOSA: Decomposition of CONCATPatrik Gustavsson
-Added support for unlimited number of dimensions -Added support for Tensors with dimension size exceeding maximum limit of NPU. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I3cc7327ac759e69042a600e686160aeb18a5ec59
2021-09-21TOSA: Decompose elem op tensorsPatrik Gustavsson
Added decomposition of tensors exceeding maximum size supported by NPU. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I17a99cb72947d2f1064a631ad6975ce895c258d5
2021-09-20TOSA: Elementwise Rank > 4 and Batch > 1Patrik Gustavsson
Added support for elementwise operations: -Support for up to Rank == 6 -Support for Batch > 1 for Rank == 4 -For binary elementwise ops this includes handling of broadcasting in dimensions above H-dimension Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I73850bbfb288077a99bd2ceecbf989172016da24
2021-09-15TOSA: Support for TABLE operator (int8)Patrik Gustavsson
Added support to map TABLE operator to LUT. Limitations: -Only supported for int8 -TABLE input must be constant This also adds the support for TFLite legalisation of Tanh/Sigmoid (int8/uint8). Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I1a95f61fb02fdd42c4a690494418cc0765c8b275
2021-09-15MLBEDSW-5102 Update removal of memory only operatorsJonas Ohlsson
Memory only operators such as Reshape, Squeeze and ExpandDims are removed in the graph optimiser step. - Added semantic check that memory only operators have same quantisation parameters on ifm/ofm. - Added support for the ExpandDims operator. - Addition and cleanup of related unit tests. - Removed TOSA from the generated SUPPORTED_OPS.md documentation. Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com> Change-Id: If848d8afc58c18806e10997ed94e4dae83f30879
2021-09-15MLBEDSW-5052 Fix RELU scalingFredrik Svedberg
Fixed scaling for RELUs with different IFM/OFM scaling. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I0ac96326b3960c0fb025b885e06a259d24b2e684
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