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2021-04-07Remove duplicate VelaError importDwight Lidman
This small commit removes a duplicate import of VelaError which causes subsequent patches to fail on the CI due to flake8 complaining at pre-commit. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Id18146511c67659b84cce0563caf0829215d5b38
2021-04-06MLBEDSW-4249 Hide stack traces in error messagesHenrik G Olsson
When faced with an invalid tflite file we now catch the exception to make it clear to the user that the issue is with the input and not with Vela, instead of just crashing. Same also applies to our own Vela error messages. Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com> Change-Id: I56a81c5be9e1f46f3b98a88c6d24ee42fa0e450d
2021-03-31MLBEDSW-4286: Bug fix Concat using IFM streamingLouis Verhaard
IFM box calculation was wrong because 2 variables were referencing/updating the same list. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: Ibed4e94c474682e14a6dd898029f14af11c9479a
2021-03-31MLBEDSW-3461: Check configuration SRAM sizeLouis Verhaard
Added check that configured SRAM size is within bounds. Change-Id: I5dce3df0788f2b00402e9a541bad11612fa19463 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-03-31Handle absent weights_compression_ration when printingHenrik G Olsson
Change-Id: Iafb31af73d80adcc901b241c34dda78be360bc14 Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
2021-03-31MLBEDSW-3502: Bug fix addresses >= 32 bitLouis Verhaard
Bug fix in generation of register command offsets that do not fit in 32 bit. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: Iabb99cf6536c0f77b934691f8744df61f1eab3ed
2021-03-30Performance improvement in tensor allocationLouis Verhaard
- Tensor allocation verification was O(N^2), is now closer to O(N) - Removed a sort in HillClimb allocator Change-Id: I286a269881490c485cc2b0eeab3b1ecffa8f3df0 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-03-30MLBEDSW-4219: Add tensor allocation info to summaryerik.andersson@arm.com
Added the theoretically minimum max memory usage and the allocator overhead to the Vela summary. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: If373dfeaac50d6f8b56554d435bf22af2c3acda3
2021-03-26MLBEDSW-4163: OFM zero point outside valid rangeDwight Lidman
This commit fixes a bug where the OFM zero point would assume values outside of [0, 255] due to it's usage as a stand-in for a bias when emulating the TensorFlow Lite implementation of MEAN. The solution is to adjust for the bias using an ADD operator with the bias value as an int16 const tensor. The 16-bit integer is needed as the bias is 32 bits in the original implementation but can effectively assume values in the range [-255, 255]. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I84df48ea89bb559954f1b2c289b65e08a6418274
2021-03-25MLBEDSW-4071: Power of two handling 16-bit tanh/sigmoidLouis Verhaard
Added special handling of power-of-two input scales for 16-bit tanh/sigmoid to align with the reference. Change-Id: I87831bcd587623d7db7100e768905355c2c98e9d Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-03-22MLBEDSW-3502: Add address checksLouis Verhaard
Added checks during command stream generation to make sure that address boundaries are respected. Change-Id: I4dbc693b42d54e35c8fcc785e8be88059e409eec Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-03-19MLBEDSW-3458: Added command stream size check.erik.andersson@arm.com
If the command stream size exceeds a certain threshold, a VelaError will now be raised. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: I9b9383f4c298a778b160cd527374e9244e4cae26
2021-03-19Address generation fixMauricio Briceno
- The architecture supports address extensions wider than 32b via the cmd1.param Change-Id: I7a01b4596f7a54f6be05b8e2c454494e6751757b Signed-off-by: Mauricio Briceno <mauricio.briceno@arm.com>
2021-03-16MLBEDSW-4215: Add support for MEAN to match QuantizedMeanOrSum implementationDwight Lidman
This commit adds support for emulating the behavior of the QuantizedMeanOrSum implementation of MEAN in TensorFlow Lite. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Ifd24e0e678e2f85cd66ab82deeaaf010d5351b1e
2021-03-16MLBEDSW-4223: Full support for PAD operatorLouis Verhaard
- Added full support for PAD operator - Hardware padding is still used whenever possible - Bug fix Pad followed by max pool if IFM contains negative values Change-Id: Ifc64d1943737d94466f5e2821009dab12a49a965 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-03-12MLBEDSW-4070: Addresses errors with the LeakyReLU operator.erik.andersson@arm.com
LeakyReLU IFMs will now have unique addresses and the alpha tensor will have correct scaling. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: If94fa91a0b61175309ac450bf6b38a63362780ab
2021-03-09MLBEDSW-4209 Use live range alignment when allocatingHenrik G Olsson
Change-Id: I05216cebe785a3669032a3f021a9b496c44c4d66 Signed-off-by: Henrik G Olsson <henrik.olsson@arm.com>
2021-03-01vela: Update release tag in setup.py2.1.1Tim Hall
- Updated tag to 2.1.1 Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I2c35557058421d2be5c934e2a1cb06a5718b4697
2021-02-25MLBEDSW-4095: Update RELEASE notes and other docs2.1.0.rc32.1.0Tim Hall
- Updated release notes - Updated supported ops - Clarified platform support - Minor clean up of README Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I62b9ff66fc7729b184a5dbb322406cfcdef4e542
2021-02-25MLBEDSW-1499: Add MEAN operatorDwight Lidman
This commit adds support for the MEAN operator, with some caveats. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I165cb26cb5aefd68e70d2cfc68291ccf7b778921
2021-02-25MLBEDSW-3571: Sum and FC should not crash when asking for keep_dims.erik.andersson@arm.com
Previously the keep_dims or keep_num_dims attribute was not supported for Sum and Fully Connected operators and would thus crash for certain tests. With this update, the attribute is extracted correctly and saved to the optimised tflite file. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: If33487f6d299bb99788bb3d13332b842ba961641
2021-02-25MLBEDSW-4064: Update copyright headerserik.andersson@arm.com
All files which have been updated in 2021 and contain a copyright header have had their headers updated. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: Ia682111a719d16e690433398ccfb69c7e93c1cd1
2021-02-19MLBEDSW-3938: Describe internal-default CLI value2.1.0.rc2Tim Hall
- Updated system config and memory mode CLI options - Fixed some formatting problems in other markdown files Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: If0fc2989538f372bfb6d6370565e940d132ca546
2021-02-19MLBEDSW-4109: Add OPTIONS section to the READMETim Hall
- Added CLI Options section. - Minor fixes to some numbering. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ic67e7010a328f0ad80992d012f3e41250642210c
2021-02-19MLBEDSW-4110: Update Pipenv configuration files for TF2.4Tim Hall
- Updated flatbuffers to 1.12.0. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ia35020dd0d554a7d1bf530251c0b443b8b7d4dfe
2021-02-17MLBEDSW-4022: support PAD followed by pool operatorLouis Verhaard
PAD followed by max/average pool is run on NPU if NPU padding can be used. Average pool is converted to depthwise. Change-Id: Icc3652e6d9ecff5ac3dc7d92080313d90c245404 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-02-17[MLBEDSW-3813] Fix LSTM operator pass throughFredrik Svedberg
Fixed pass through of LSTM operator. Change-Id: I23140c69ab6cdc83f6bb8129256b4cc6a7c5ffac Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2021-02-16MLBEDSW-4076 Fix read_offset at create_primary_opPatrik Gustavsson
Fix read_offset at create_primary_op The read_offset need to be copied when adding avg pool as primary operator. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I6f168517a0e22543455b623b6b4f59237e8d530a
2021-02-16Make HillClimb allocation reproducibleFredrik Svedberg
Made HillClimb allocation results reproducible between runs. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I0535947e9cd9c6e0cf896e81b127d93cab54ebc8
2021-02-16Corrected the help string of --force-block-configJacob Bohlin
Made the same correction in OPTIONS.md Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: If79ee5c4c7464b40a72bbe6871b52a9eb0b308e1
2021-02-12MLBEDSW-3808: Ported search allocator to python2.1.0.rc1Louis Verhaard
- Straight port of the C++ implementation to python. - Renamed the allocator from "Search" to "HillClimb" Change-Id: I50797d541f326d0264daf79bf7866aef32350a60 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-02-12MLBEDSW-3509: Updated the debug database to support multiple custom operators.erik.andersson@arm.com
Previously the debug database lost some operators in the debug database outputs when multiple custom operators were generated by Vela. Also, the file offsets for command streams were always 0, even for a single custom operator. This patch should rectify these problems. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: Ieb072440d4f1806d4833a676683b4f42f431f3df
2021-02-12MLBEDSW-3902: Fixes invalid op when cloning LeakyReLU operatorerik.andersson@arm.com
When running specific networks containing LeakyReLU operators, Vela would crash when cloning an ofm of a LeakyReLU operator. In this procedure a deepcopy usage would try to copy an OperatorInfo object, which caused an error. This was fixed by replacing the deepcopy usage with a copy and then manually referencing new instances of sensitive variables. Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com> Change-Id: I46917858896fbdf52245dac6c6d9c18bc7ecdd0d
2021-02-12MLBEDSW-3600: Cascading support for ResizeBilinearJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I7899263ff5bb3d0de00681ee8351a02eecff1553
2021-02-11MLBEDSW-3774 Fix avoid cascading for spillingPatrik Gustavsson
Fix avoid cascading for spilling. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: If86189bd1566eaa14387dfc2c02e3324ea6c184e
2021-02-11MLBEDSW-3774 Remove SplitSliceReadPatrik Gustavsson
Removed SplitSliceRead from subgraph during graph optimisation. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I9315d4c2a6767828dd2b4e66823d73b10ebee99c
2021-02-09MLBEDSW-3774 Removed ConcatSliceWritePatrik Gustavsson
-Removed ConcatSliceWrite from the optimised graph. Always executed as avgpool, which is equivalent with before the patch. -Added copy op to enable more removal of reshapes. Sg input/outputs need to remain. When Reshape input and outut, are sg input/outputs a copy op is needed to be inserted, in order to remove the reshape. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Id7be9966673ae34499e8518a5544104493fe326b
2021-02-08MLBEDSW-3937 Fix check for NHCWB16 for FCPatrik Gustavsson
Fix check for NHCWB16 for modifying FC input. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: Ie50c32ca079afadd0af9b7b909820794ceee373c
2021-02-08MLBEDSW-3953: Output diff in mobilenet_v3Diqing Zhong
Fixed two issues: - Cmd stream can be out of order in Ifmstreaming - In H32, LUT could be corrupted if blockdep is not 0 Change-Id: I2edd84429b93d83b2794f14937ce3fd279fd4a24 Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2021-02-05MLBEDSW-3771: Updated to TF 2.4 flatbuffer schemaTim Hall
Updated tflite loader and mappings from tensorflow 2.3 to tensorflow 2.4 Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I55884000ee139baf639bb0377008e0534f72fe94
2021-02-05vela: Change Shape4D mutability usageTim Hall
- Removed requirement for cloning shapes when unique values required by forcing top-level immutability. This alleviates issues with Shapes being unintentionally shared and then mutated as if value-types. - Shape4D fields can no longer be assigned without replication. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ic0dbfa349eb0215eabefb4f4e2cf99f12d83699c
2021-02-05MLBEDSW-3772 Removed fixup_act_reorderPatrik Gustavsson
Removed fixup_act_reorder from graph optimisation. As Reshape ops has been removed this optimization should not be needed. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I2c375ee7787bf15f66c1e16514ed62727934d869
2021-02-04MLBEDSW-3937 Fix moving FM to fast storagePatrik Gustavsson
Featuremaps were never moved to fast storage when tensor is set to not use NHCWB16. This patch enables the evaluation of feature maps to be moved fast storage, also when tensor use NHWC. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I6367c975e7af8739c774cb7c34b43fb9a6776c8c
2021-02-04MLBEDSW-3932: Remove Squeeze from supported operatorsLouis Verhaard
- Squeeze is no longer listed as supported operator - Added missing doc-string for a Pad constraint Change-Id: Ifd5e493acb0eb28bc4f104df74b3491589db8c29 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-02-04MLBEDSW-3951 Consider reshaping in pass packingPatrik Gustavsson
Consider reshaping in pass packing, when desiding if operators can be packed. For the cases where there is a reshape between ops they cannot be fused. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I8f2833b3fff156e9633ce0189d1d0df9109a6622
2021-02-03MLBEDSW-3572: Fused activations must not be int32Louis Verhaard
Added supported operator check that 32-bit fused activation functions are not supported. Change-Id: I01fdafeff8fdb13c71eae4f63be7e6f81b9223df Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-02-02MLBEDSW-3927: Fix wrong compression ratioDiqing Zhong
Change-Id: I06feeb98fb48badf06097f377a9504e6f4eeae91 Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
2021-02-02[MLBEDSW-1743] Fix scaling for Abs operatorFredrik Svedberg
Fixed the scaling for the Abs operator. Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com> Change-Id: I9c198547de18f1268bfc2cb2f3d79cb30de4f43e
2021-02-01MLBEDSW-3903: Bug fix PAD operatorLouis Verhaard
- Added checks for unsupported pad sizes in PAD operator - Bug fix right pad/bottom pad calculation when replacing PAD operator by hardware padding Change-Id: Ib84be711277d987052f14352ab386e0e0b774987 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2021-01-29MLBEDSW-3224: Support HardSwishDiqing Zhong
Change-Id: If49abc31f093f1bd3393bee86f821fd35972086f Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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