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- The failing tests contain operations with dynamic tensors which
are not supported and therefore they should be placed on the CPU.
However, a bug in the removal of RESHAPEs which contain a dynamic
shape prevented this happening.
- This change adds a check to make sure that RESHAPE ops with a
dynamic shape tensor are not removed and instead are placed on the
CPU.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I2d7481f7f80f99a0f01df100d956933777e6875a
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This commit adds the author_email field with email
address <mlg-vela@arm.com> to the
setuptools.setup() function in setup.py.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: If3b2605ea9b05a8a4c6f899d8af77cbaec9ce9b5
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Change-Id: I645496536a6bddf2bd289a87be9d7cef11693954
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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* 1D optimised block_config was incorrectly beign set to the ArchitectureBlockConfig in try_block_config()
* Write external API test for the reduced block height case (on H256)
Signed-off-by: James Ward <james.ward@arm.com>
Change-Id: I9ced7eb31b23730e4423aabbaf769bc72fac8fc9
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This reverts commit 0af0d383925968626a7c37,
which caused a regression by rejecting
previously passing tests as faulty.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: If11737713b6873a67162387e407eadf174b434ec
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* Add small aesthetic changes to summary
* Move "_cpu" suffix from cloned tensor to original tensor such that suffix is no longer externally visible
Signed-off-by: James Ward <james.ward@arm.com>
Change-Id: I97427561bd9acb04765ae9de6278760511278118
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Fixed by adjusting zero points for ops with int8 IFM and asymmetric weights
since the reference does not support asymmetric weights for int8 IFM and
ignores the zero points.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I2a206a01a471a53aa864a6a3616aa23d2a5a23c8
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- Back-to-back 16-bit activation ops were packed into the same pass
because there was no check to disallow it
- The solution is to set the appropriate incompatible-flags
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Idb3c741a7b52e0d81c1f687f6ecf78352b7872dd
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Previously we did not check if half_pixel_centers
was set. Since we do not support it, these cases
should not run on the NPU.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: I9d2675f760424d5cfb67e5d581dd1861ad165b85
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* Add check for tensor with no operations, raising error if its constant-data buffer is empty
Signed-off-by: Alex Matthews <alex.matthews@arm.com>
Change-Id: Ib210dcc9733e4ecedbada0f430e8b3c4a8384999
Signed-off-by: James Ward <james.ward@arm.com>
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Change convert_pad optimiser to use op.ifm_shapes attribute in place of
the fickle op.ifm.shape (which in this case had changed due to the
optimised-out reshape)
Signed-off-by: James Ward <james.ward@arm.com>
Change-Id: I13fbd846ac8d3342afd7844d1041cfa15aaae124
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Added checks to avoid merging elementwise op live ranges for subgraph
inputs and outputs, which sometimes caused problems when parts of the
network run on CPU.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: Id07ab277a205b8550d19a276559f8904b9a4b4be
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Make sure unsupported memory only operations are issued
to the CPU.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: Ifdf7c3056ab45d707db5b67113549a73133b69c8
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Fixed crash in nn_graph.print_graph_with_tensors() and
nn_graph.print_graph_with_tensor_quantization() for optional
input tensors.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I7a2d23892558006485c5c84842d65aa221dba44b
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This commit fixes a number of bugs where per-axis
quantization would make Vela crash and would not
be properly recognized.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I50a461d200274b43ec76f3a7357bf66db6d49964
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* fix indices for tflite mapping of EXP operator
* fix indices for tflite mapping of Transpose operator
* ensure read offset after slice is aligned to 16 bytes for NHCWB16 or force linear format
* add unit test to ensure mapping of indices is consistent across TFLite, TOSA and NNG
Signed-off-by: James Ward <james.ward@arm.com>
Change-Id: I17b6e44bc06853325d5eea62a558418ee1ebefe8
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Removed graph optimizations no longer needed that caused problems
with FullyConnected operators running on CPU being consumed by
elementwise operators in Vela.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: Ic7e66141ccd5e9aa8f0022c5ab9e7fd1ba3f6786
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This commit fixes an issue where networks with
multiple CPU-placed subgraphs would crash due
to the assumption that the second subgraph is
always placed on NPU.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Ib7e7a9e89d3b0f3a597cf80446f5eb8b132883a4
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This commit add some TensorTypes that were missing
to the TensorFlow Lite mapping.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I15e80769491e8f3093c14270cf2e312f1568dfc8
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Adds a constraint on batch size for the MEAN
operator. Due to the restrictions imposed by the
NHCWB16 format, some operators do not allow batch
sizes larger than 1. The MEAN operator uses the
operators in its implementation, but the
constraint was missing and thus the operator was
being wrongly placed on the NPU.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I95e07a9151a6a131c337caa3114da1154be39e49
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Added support for a Const operator generating
network output.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ia81990a94cc497a58535914124a29e7dbb511247
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Fixed regression when the AveragePool has explicit rescaling.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I121a0cbf9ab15c8862739266e088b5db7805446b
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Fixed zero point issue for AveragePool with fused RELU activation.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I1810752d4575b12ec3dcb67637dc505a62ac5607
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Update based on schema corresponding to
TOSA conformance tests release v0.5.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I517cd5d86ddb3ed8c0f377b4462466387dc3af44
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Added support for:
-Rank > 4 and batch > 1
-Tensor dimensions exceeding NPU limit
-Padding in any dimension
(Implementation for functional compliance,
not considering performance)
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ief58fb3233d885f10ba5e68c5374b190efbe9351
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Resolves a bug where an IndexError would occur
if the same tensor was assigned to both IFM
and IFM2 of a binary elementwise operator
due to duplicates being allowed in operator
inputs but not in pass inputs.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I39a6206a6252f6a848be9f9d4c5a8dc749c71699
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Added support for Identity operation.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: If00b30528932f7531807ce3914d6c1875ab72fa4
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Fixed output diff for some architectures due to incorrect IFM buffer size
calculation when using NearestNeighbour upscaling.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I0d6d1efc606603cdd6188ae282e7f6babfd7e24e
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-Added support for unlimited number of dimensions
-Added support for tensors exceeding maxlimit of NPU
-Fixed regression for PAD
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ib2ce50a30cc5cf396032d85d57dab9968e3fc06a
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-Added support for unlimited number of dimensions
-Added support for Tensors with dimension size
exceeding maximum limit of NPU.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I3cc7327ac759e69042a600e686160aeb18a5ec59
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Added decomposition of tensors exceeding
maximum size supported by NPU.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I17a99cb72947d2f1064a631ad6975ce895c258d5
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Added support for elementwise operations:
-Support for up to Rank == 6
-Support for Batch > 1 for Rank == 4
-For binary elementwise ops this includes handling
of broadcasting in dimensions above H-dimension
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I73850bbfb288077a99bd2ceecbf989172016da24
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Added support to map TABLE operator to LUT.
Limitations:
-Only supported for int8
-TABLE input must be constant
This also adds the support for TFLite legalisation of
Tanh/Sigmoid (int8/uint8).
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I1a95f61fb02fdd42c4a690494418cc0765c8b275
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Memory only operators such as Reshape, Squeeze and ExpandDims are
removed in the graph optimiser step.
- Added semantic check that memory only operators have same
quantisation parameters on ifm/ofm.
- Added support for the ExpandDims operator.
- Addition and cleanup of related unit tests.
- Removed TOSA from the generated SUPPORTED_OPS.md documentation.
Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com>
Change-Id: If848d8afc58c18806e10997ed94e4dae83f30879
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Fixed scaling for RELUs with different IFM/OFM scaling.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I0ac96326b3960c0fb025b885e06a259d24b2e684
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- Re-added the CustomOptionsSerializer to the CUSTOM op TFLite mapping
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I51b141749ba223c132190077eed9e22fac798d2d
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Added support for standalone CLAMP/RELU.
Limited to:
-Rank <= 4
-N = 1 if Rank = 4
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: If1a32fb330ce6c67c09ec4b554b4a0688444d5f0
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Added support for TOSA PAD operator
in line with legacy support
Limitations:
-Rank <= 4
-N = 1 if Rank = 4 for ifms/ofm
-only padding in W and H dimensions
-bool_t not supported
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I511608202b4c9bf6d86285b559c517fb41741fdf
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-Only support for avgpool when there is
no padding. For this case, global scaling can be used.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I026b83b05f02c57c79f49935f5ec501a6d28bb91
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Added support for Data layout ops
RESHAPE, SLICE and CONCAT.
-No support for bool_t
-Support limited to Rank <= 4 and N = 1
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I487ac494b6506a2a6ba947ee758aa193194dd796
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Additional check added for when constant data can be moved
to fast storage.
Do not move constant data for concat.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ib8b5fd1483ee9fabe48e9874a5723af9b7c5231a
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This commit fixes one assert regarding rolling buffers for 3D tensors.
It also addresses another issue where the incorrect weight buffering was
proposed for cascaded operators.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I2501f35e5668b3085d917751cfc8002d250973d8
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Added support for ADD, SUB and MUL
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I52acdc126b16e2cf4096bcf7a77023ea7d204998
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This is mainly to add support for depthwise conv2d
with dephmultiplier = 1.
(But there are no testcases suited, all I have sourced
has depth_multiplier set to 2, which is not supported.)
-Added support for depthwise conv2d.
-Added support for removing Transpose of constant data
-Added support for removing reshape
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I143e6246becfa78fd9f7510af0bf0d6b3fbbf2c7
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Fixed output diff for wav2letter int16 by correcting the scaling
used for LeakyRelu.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I8be1e14c25d223dc6e42c4ec498ff4d3d9de65d7
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Added support for
-AVGPOOL and CONV2D with TFLite correspondence
-MAXPOOL
-additional support for replacing RESCALE ops with avgpool.
No support for breaking down tensors over the
size supported by NPU.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I1d2aa50ac30a26283b3e6f1fe88cba1544b7c189
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- Add TOSA output generation in npz format
Change-Id: I97822e3a93a8fef1a95a990f23ef2c4ca5a8f73a
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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This commit contains the release notes
for Vela 3.1.0. It also increases the
PyPI documentation tag.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Iffd9fac7d4a7ccb34c3558990ef4bb97e548bf4c
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Update to handle the case when the Squeeze Op ifm/ofm are the
subgraph ifm/ofm, to facilitate the removal of the Squeeze Op.
Adding NOP to maintain the original tensors.
Updated pytests for squeeze operator.
Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com>
Change-Id: I623cae05e696fb16ccf29dedc42fd822601e9fd9
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Updated the README.md to include some examples of
new scheduler modes.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: Ifa1a9a69b94ab37efa3aac7e82bb89e0e3a25b85
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