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* fix indices for tflite mapping of EXP operator
* fix indices for tflite mapping of Transpose operator
* ensure read offset after slice is aligned to 16 bytes for NHCWB16 or force linear format
* add unit test to ensure mapping of indices is consistent across TFLite, TOSA and NNG
Signed-off-by: James Ward <james.ward@arm.com>
Change-Id: I17b6e44bc06853325d5eea62a558418ee1ebefe8
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Removed graph optimizations no longer needed that caused problems
with FullyConnected operators running on CPU being consumed by
elementwise operators in Vela.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: Ic7e66141ccd5e9aa8f0022c5ab9e7fd1ba3f6786
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This commit fixes an issue where networks with
multiple CPU-placed subgraphs would crash due
to the assumption that the second subgraph is
always placed on NPU.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Ib7e7a9e89d3b0f3a597cf80446f5eb8b132883a4
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This commit add some TensorTypes that were missing
to the TensorFlow Lite mapping.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I15e80769491e8f3093c14270cf2e312f1568dfc8
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Adds a constraint on batch size for the MEAN
operator. Due to the restrictions imposed by the
NHCWB16 format, some operators do not allow batch
sizes larger than 1. The MEAN operator uses the
operators in its implementation, but the
constraint was missing and thus the operator was
being wrongly placed on the NPU.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I95e07a9151a6a131c337caa3114da1154be39e49
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Added support for a Const operator generating
network output.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ia81990a94cc497a58535914124a29e7dbb511247
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Fixed regression when the AveragePool has explicit rescaling.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I121a0cbf9ab15c8862739266e088b5db7805446b
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Fixed zero point issue for AveragePool with fused RELU activation.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I1810752d4575b12ec3dcb67637dc505a62ac5607
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Update based on schema corresponding to
TOSA conformance tests release v0.5.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I517cd5d86ddb3ed8c0f377b4462466387dc3af44
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Added support for:
-Rank > 4 and batch > 1
-Tensor dimensions exceeding NPU limit
-Padding in any dimension
(Implementation for functional compliance,
not considering performance)
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ief58fb3233d885f10ba5e68c5374b190efbe9351
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Resolves a bug where an IndexError would occur
if the same tensor was assigned to both IFM
and IFM2 of a binary elementwise operator
due to duplicates being allowed in operator
inputs but not in pass inputs.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I39a6206a6252f6a848be9f9d4c5a8dc749c71699
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Added support for Identity operation.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: If00b30528932f7531807ce3914d6c1875ab72fa4
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Fixed output diff for some architectures due to incorrect IFM buffer size
calculation when using NearestNeighbour upscaling.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I0d6d1efc606603cdd6188ae282e7f6babfd7e24e
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-Added support for unlimited number of dimensions
-Added support for tensors exceeding maxlimit of NPU
-Fixed regression for PAD
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ib2ce50a30cc5cf396032d85d57dab9968e3fc06a
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-Added support for unlimited number of dimensions
-Added support for Tensors with dimension size
exceeding maximum limit of NPU.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I3cc7327ac759e69042a600e686160aeb18a5ec59
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Added decomposition of tensors exceeding
maximum size supported by NPU.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I17a99cb72947d2f1064a631ad6975ce895c258d5
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Added support for elementwise operations:
-Support for up to Rank == 6
-Support for Batch > 1 for Rank == 4
-For binary elementwise ops this includes handling
of broadcasting in dimensions above H-dimension
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I73850bbfb288077a99bd2ceecbf989172016da24
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Added support to map TABLE operator to LUT.
Limitations:
-Only supported for int8
-TABLE input must be constant
This also adds the support for TFLite legalisation of
Tanh/Sigmoid (int8/uint8).
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I1a95f61fb02fdd42c4a690494418cc0765c8b275
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Memory only operators such as Reshape, Squeeze and ExpandDims are
removed in the graph optimiser step.
- Added semantic check that memory only operators have same
quantisation parameters on ifm/ofm.
- Added support for the ExpandDims operator.
- Addition and cleanup of related unit tests.
- Removed TOSA from the generated SUPPORTED_OPS.md documentation.
Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com>
Change-Id: If848d8afc58c18806e10997ed94e4dae83f30879
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Fixed scaling for RELUs with different IFM/OFM scaling.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I0ac96326b3960c0fb025b885e06a259d24b2e684
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- Re-added the CustomOptionsSerializer to the CUSTOM op TFLite mapping
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I51b141749ba223c132190077eed9e22fac798d2d
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Added support for standalone CLAMP/RELU.
Limited to:
-Rank <= 4
-N = 1 if Rank = 4
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: If1a32fb330ce6c67c09ec4b554b4a0688444d5f0
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Added support for TOSA PAD operator
in line with legacy support
Limitations:
-Rank <= 4
-N = 1 if Rank = 4 for ifms/ofm
-only padding in W and H dimensions
-bool_t not supported
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I511608202b4c9bf6d86285b559c517fb41741fdf
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-Only support for avgpool when there is
no padding. For this case, global scaling can be used.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I026b83b05f02c57c79f49935f5ec501a6d28bb91
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Added support for Data layout ops
RESHAPE, SLICE and CONCAT.
-No support for bool_t
-Support limited to Rank <= 4 and N = 1
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I487ac494b6506a2a6ba947ee758aa193194dd796
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Additional check added for when constant data can be moved
to fast storage.
Do not move constant data for concat.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: Ib8b5fd1483ee9fabe48e9874a5723af9b7c5231a
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This commit fixes one assert regarding rolling buffers for 3D tensors.
It also addresses another issue where the incorrect weight buffering was
proposed for cascaded operators.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I2501f35e5668b3085d917751cfc8002d250973d8
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Added support for ADD, SUB and MUL
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I52acdc126b16e2cf4096bcf7a77023ea7d204998
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This is mainly to add support for depthwise conv2d
with dephmultiplier = 1.
(But there are no testcases suited, all I have sourced
has depth_multiplier set to 2, which is not supported.)
-Added support for depthwise conv2d.
-Added support for removing Transpose of constant data
-Added support for removing reshape
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I143e6246becfa78fd9f7510af0bf0d6b3fbbf2c7
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Fixed output diff for wav2letter int16 by correcting the scaling
used for LeakyRelu.
Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: I8be1e14c25d223dc6e42c4ec498ff4d3d9de65d7
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Added support for
-AVGPOOL and CONV2D with TFLite correspondence
-MAXPOOL
-additional support for replacing RESCALE ops with avgpool.
No support for breaking down tensors over the
size supported by NPU.
Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I1d2aa50ac30a26283b3e6f1fe88cba1544b7c189
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- Add TOSA output generation in npz format
Change-Id: I97822e3a93a8fef1a95a990f23ef2c4ca5a8f73a
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
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This commit contains the release notes
for Vela 3.1.0. It also increases the
PyPI documentation tag.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Iffd9fac7d4a7ccb34c3558990ef4bb97e548bf4c
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Update to handle the case when the Squeeze Op ifm/ofm are the
subgraph ifm/ofm, to facilitate the removal of the Squeeze Op.
Adding NOP to maintain the original tensors.
Updated pytests for squeeze operator.
Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com>
Change-Id: I623cae05e696fb16ccf29dedc42fd822601e9fd9
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Updated the README.md to include some examples of
new scheduler modes.
Signed-off-by: erik.andersson@arm.com <erik.andersson@arm.com>
Change-Id: Ifa1a9a69b94ab37efa3aac7e82bb89e0e3a25b85
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To avoid using Python 3.6 incompatible versions of NumPy (> 1.19.5),
an upper bound on version is added for NumPy in setup.py.
Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com>
Change-Id: I3929bd7dbea6866905665186af1c4b3ba43ccbd0
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A commit pertaining to MLBEDSW-4738 where the
functionality of find_block_configs() in the
external API was reinstated had previously been
merged, but was done without increasing the API
version. This commit amends that mistake.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I32f559d626e0f4e93c522813b6f4e12beaa50e57
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This commit adds a CLI option for setting
the recursion limit. This option was originally
removed because it was considered unnecessary,
but in some cases of very large (enormous) networks,
a RecursionError is encountered during graph traversal.
A simple solution for issues like those is to manually
increase the recursion limit.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Id0dbf68edf59b151abfa91783b5f8f021c1bb40f
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Bug fix in cascade builder: tensors produced with operators requiring full OFM
or consumed by operators requiring full IFM could be added as intermediate buffers
to a cascade.
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Change-Id: Id84e9e1940bf85ab4cbc42a03e65f64da16a094c
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- Deleted file as it was no longer needed
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I03df2fc98964b96f4c7eabcf98dd5baa19de78ca
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Fix inception_v1/v3 output diffs.
Removing the Squeeze operator in the graph optimisation step.
The squeeze operator removes dimensions of size 1 from tensor shape.
The memory layout is preserved.
Signed-off-by: Jonas Ohlsson <jonas.ohlsson@arm.com>
Change-Id: I4ceffcbb141af5ed50b0d1a9d1d67622e638c2a1
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- Fixed index error in memory_snapshot
- When removing a cascade, also references are removed
Change-Id: I2b35dc52671d8ce115eb32bfdd93584391d1fc6d
Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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option""
This reverts commit 257a31e93cb2c7a8c06a102211ebb05b3ba78cd8.
Reason for revert: <INSERT REASONING HERE>
Change-Id: If4f565d8c692e2b32903819561591d9e4af619fa
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Relationship to other patches
This reverts commit b6dd9c2e5fcf2885fb42dab567378c8aec22215c.
Reason for revert: <INSERT REASONING HERE>
Change-Id: I50afb5ac4e33e5b8cd4f2aac1f5b94700ab8eeb1
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- Changed mem_type_size() to only return a hard limit
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: Ia9271c54a592965f88f52fe25a52b3efaca88500
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Fixed a bug that caused the constant and buffered weights to expect
different encoding.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I77acee29d104bc7c8e132907e61a72b581ace0e5
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Reinstated the v2.1.0 functionality for find_block_configs(). This is
used exclusively by the external API.
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
Change-Id: I6977f13866957edb083769658cc8c57c2b3556fb
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This commit moves a piece of code back into a loop
but with a flag to make sure that the code is only
executed once per loop rather than potentially every
iteration. This solves the issue of an output diff
because of LUT DMAs occurring before weight DMAs.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: I3e597f0a955154af3d87febacea1b3920d53b7c2
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Previous to this commit some networks were failing due
one or more options in the TFLite mapping being
incorrect after the update to match TF 2.5.
This commit reverts those changes.
Signed-off-by: Dwight Lidman <dwight.lidman@arm.com>
Change-Id: Ia0b577ca44d76486fc3e0ea9780e0dc1d2baf65e
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- Changed Ethos-65 AXI port address width from 48 to 40-bits
- Fixed the use of arena_cache_size in mem_type_size() to cover the
arena as well as the cache memory area
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I826462a0cbd0c061cccbc7c83dde446778a2b1ca
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