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2020-06-30MLBEDSW-2575: Update documentation for Yoda Beta1.1.0.rc21.1.0Tim Hall
- Added release information - Added PyPi documentation Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Iaae64cfe10a2fa65f0559d13940b19d6f57edfdc
2020-06-26MLBEDSW-2552: Skip npu cycle calculation for cpu op1.1.0.rc1Charles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: Ief50c934b9e9b0bd3024d3ed0bbaa7b655971952
2020-06-25MLBEDSW-2556: Odd core/block depth weight interleaving updateTim Hall
- If blockdepth or core count resulted in empty or non-existent substreams, the command generator generated an error. This commit changes the command stream generator to only program cores that have streams and are enabled for the configuration. Change-Id: I4e724b19de14d3a12e886ec6b17d0038593dfb59 Signed-off-by: Tim Hall <tim.hall@arm.com>
2020-06-25vela: MLBEDSW-828 weight/scale stream interleavingTim Hall
- Multicore weight and scale stream interleaving for multicore hardware architecture. Change-Id: Ic82850463391c629d90d08c26cf0c48dd438286d Signed-off-by: Tim Hall <tim.hall@arm.com>
2020-06-25MLBEDSW-2306 Added more supported mem-cfgsPatrik Gustavsson
Additional supported memory configurations: -Permanent_storage = DRAM -Tensor arena either in DRAM or SRAM Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I20beb7151e306bfdba540e7c0b2a7b478b4d94e1
2020-06-23MLBEDSW-2547 Add accelerator_configsPatrik Gustavsson
Added more accelerator configs. Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com> Change-Id: I77a5ece0b9ed1eddb9b8aa9bb7656a022df95fd6
2020-06-23Update arch to 1.0.1Douglas Troha
- Includes npu_active event Signed-off-by: Douglas Troha <douglas.troha@arm.com> Change-Id: I9a2e342a11b9cc2a51f42141edb6f1a4fb4725e7
2020-06-23doc: Add PyPi information to README.mdTim Hall
- Added PyPi installation info - Added source code download/cloning info - Updated development status in setup.py Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I5c2f7dfe19a222f008b5f825c58d0fec14792bc1
2020-06-18doc: Remove remains of a merge-conflict in OPTIONS.md1.0.0Jacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: Id6dc0aac1b8b493d65c9c8ea132f5c4b5e273654
2020-06-18vela: Fix block config override issue.Tim Hall
- A blanket exception was preventing block config overrides from being used, from either code or command line. Change-Id: I1a7aa7771e077bcdb66886a6b637d099ae43d732 Signed-off-by: Tim Hall <tim.hall@arm.com>
2020-06-18MLBEDSW-2528: MLCE-219: Custom operator pass throughTim Hall
- Fixed custom operator pass through - Added error printing functions for operators and tensor - Minor cleanup of custom exception handling Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Idf295df1e4c544381dc480244d880c32fb285e38
2020-06-18MLBEDSW-2062: Add EAC release notesTim Hall
- Added RELEASES.md - Updated testing and contributions Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ia5ca3e11f03f03b739d1ce132ee001d5feb2c19e
2020-06-18MLBEDSW-2506: Swap broadcast input if applicableCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: I6e8a97486aa2e1a21101f7cc32cd3024a376162a
2020-06-18Code clean-up using black and flake8Tim Hall
- No functional change Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I5ab1198b9d092cd041fa9b85b2dee9900d299bfc
2020-06-18tools: Fix pytest-cov in pre-commitTim Hall
- Corrected name in config file Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I245571605173466d08ea2a2139444fc9ff519d3b
2020-06-18MLBEDSW-2436: Support for HardSwish operatorLouis Verhaard
- Added support for HardSwish (placed on CPU) - Improved error reporting for unknown operator codes in input file Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: I1d1c7b9d786288d7098450cdad2b67fc0759378b
2020-06-18MLBEDSW-2432: Retain pass order for CPU subgraphCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: I92b18262608415e84266d2903e17fc5112793a38
2020-06-18Added --nhcwb16-between-cascaded-passes to OPTIONS.mdJacob Bohlin
Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I99e58d22ec26cf573f5f8b567393e515b2c43794
2020-06-18MLBEDSW-2435: Fix for cascading upscaling operatorsJacob Bohlin
Fixed a coordinate issue which caused the compiler to crash when cascading upscaling operators such as ResizeBilinear. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: I982863573b0e5829e6d0c255dbbc308cb332a37a
2020-06-18MLBEDSW-2468: Rounding 16bit scale multiplier by 0.5Charles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: I78f475f9837a7c11f01b2693b17efe1a7c6481cc
2020-06-18MLBEDSW-2370: Add CLI option for NHCWB16Charles Xu
Make it configurable for using NHCWB16 between cascaded passes. Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: I259cdaa424d11ea38f17e671490ad1e630bbae44
2020-06-18MLBEDSW-2475: leaky relu not handling negative alpha valueDwight Lidman
This commit places LeakyReLU operators with a negative alpha value on the CPU and avoids a crash during command stream generation. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: Iac68c5a9fdbf26facb709660965615b2b5b551f9
2020-06-18MLBEDSW-2061: Document CLI OptionsJacob Bohlin
Updated OPTIONS.md, containing documentation regarding the CLI options and the system configuration file. Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com> Change-Id: Idd278e9fe4cd83f13c4b15430421ec22d7f4e465
2020-06-18MLBEDSW-2455: Bug fix int16 elementwise with scalarLouis Verhaard
Bug fix in the generation of the NPU_SET_IFM2_SCALAR parameter. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: Ie261a90dcfa61ed269d27a100eb48c58af8a325d
2020-06-18MLBEDSW-2379: Fix 1-element tensors that were marked as scalarsLouis Verhaard
Tensors that are the result of an operation were incorrectly marked as scalars. Also fixes a bug for IFM2 of shape [*,*,*,1] in elementwise operations. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: I82a0e643b12e93c7158e4aca3185415c59033a73
2020-06-18MLBEDSW-2471: Remove unused CLI optionsTim Hall
- Removed --inter-pass-cycle-delay - Removed --dram-bandwidth - Removed --batch-size Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ib613f47a9e911c652e522b5aa9ec58ae5391b0fd
2020-06-18MLBEDSW-2063: Add contributions guidelinesTim Hall
- Create new CONTRIBUTIONS.md - Rearrange README.md to reference new documentation Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I502b1606a3fe829a9e242a5de7391bf769203b8c
2020-06-18MLBEDSW-2388: Bug fix cascaded poolingLouis Verhaard
Kernel height was not correctly calculated for pooling operations in rolling_buffer_dims_from_passes. Change-Id: I48763b4b3276538c111e6699f66636327e569705 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-06-18vela: Fix tensor purpose for some CPU only opsTim Hall
- Add support for marking the tensor purpose of CPU only ops such as LESS which mark their input based upon their output Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ia7898089f0b18ccd4f183e2ef961a67f4d169e4c
2020-06-18MLBEDSW-1828: Ifm/ifm2 order is reversed in some cases of splitCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: Ib8d66f8b3c0467966165c1b53aeb7da7c8764c89
2020-06-18MLBEDSW-2232: Update Readme with security infoTim Hall
- Create new SECURITY.md Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: Ia2885300e488355057b3bbcd8eb6873d82599708
2020-06-18vela: Add support for CPU only networksTim Hall
- Fix various problems when no operators run on Ethos-U55 Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I44a1a914fabb7ca26c921a02753da8abeecd9c7b
2020-06-18MLBEDSW-1716: Transpose Convolution supportJacob Bohlin
Change-Id: Ie6d8d6de9f3447f19ba06aafa9fa480fc96a973b Signed-off-by: Jacob Bohlin <jacob.bohlin@arm.com>
2020-06-18MLBEDSW-2269: Fix the buffer overlap issue for multi subgraphesCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: Ia7127148d00280bf9c3759dd6dcbe500a4cfcc78
2020-06-18MLBEDSW-2420: Improved support for dilated convolutionLouis Verhaard
- Dilation added to SET_KERNEL_STRIDE instruction - Kernel height/width adjusted for dilation - Updated padding calculation - Updated weight compression Change-Id: I0c8190223e223b039a305aba0f37896ae1de2b80 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-06-18MLBEDSW-1941: Bug fix shared weightsLouis Verhaard
If same weight tensor was used with different block configs, errors would occur. Fixed by always cloning weight tensors, using a global weight compression cache and modifying the linear allocator to detect multiple usage of same weight compression. Change-Id: I91ca59176e1c59c66e0ac7a4227f2b5f0b47053f Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-06-18MLBEDSW-2434: optim: 19_12_32, bilinear + depthwise int8 output diffDwight Lidman
This commit fixes a bug where there would be an off-by-one error in some cases for ResizeBilinear. It is resolved by treating it the same way as an AvgPool in regards to setting the zero point. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I2835d5dcf360f65e19265c339e5ffd02de16c823
2020-06-18MLBEDSW-2372: Failing assert for ResizeBilinear with upscale != 2xDwight Lidman
This commit fixes the failing assert by removing it and instead placing unsupported ResizeBilinear operators on the CPU. It introduces a new graph optimisation function which adds the necessary attributes as well as new operator restrictions for ResizeBilinear. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I2feffd0b5a2169ebffbe4f165e450b3f2d140380
2020-06-18MLBEDSW-1971: Verify ifm block size calculation against specificationDwight Lidman
This commit ensures the IFM block size calculation in architecture_features.py matches the specification by correctly setting the ifm upscaling factor based on the upscaling mode. This requires adding an attribute to the Tensor object which stores the upscaling mode for that specific tensor and making sure that information is correctly carried over to shared_buffer_allocation.py. Signed-off-by: Dwight Lidman <dwight.lidman@arm.com> Change-Id: I4ab56086f4c694d3bf759bbad30cdb969b4a26db
2020-06-18[MLBEDSW-1996] Update supported operator checksFredrik Svedberg
Updated supported operator checks according to latest requirements. Change-Id: I79708d8039e464e39818d3c09e61f3f533e96f3d Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-06-18MLBEDSW-2339: No DMA needed for elementwise scalar in case of offchipCharles Xu
Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: I7b18af503ac6482cf8dc3e9f3e2e93e6cba6426f
2020-06-18MLBEDSW-2067: added custom exceptionsLouis Verhaard
Added custom exceptions to handle different types of input errors. Also performed minor formatting changes using flake8/black. Change-Id: Ie5b05361507d5e569aff045757aec0a4a755ae98 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-06-18Add elementwise vector scalars supportCharles Xu
Write the constant scalars into flash. In case it's Dram or OffChipFlash, DMA the scalars from flash to sram. Signed-off-by: Charles Xu <charles.xu@arm.com> Change-Id: I42300a05dfe968d623b8aec8549644549e0f54b5
2020-06-18MLBEDSW-786: Fix Tanh/Sigmoid for int16Fredrik Svedberg
Fixed scaling for int16 tanh/sigmoid to match the reference. Change-Id: I3110298b7e8638a82cc05bedc03de389dec27898 Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
2020-06-18MLBEDSW-1540: bug fix SHRAM buffer size calculationLouis Verhaard
Updated the algorithm for SHRAM buffer size calculation with block depth alignment. Change-Id: Ie8b10725bb9f52ba4a353b5a2170653833e6e5c0 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-06-18MLBEDSW-2002: Fix Reshape's output MemAreaLouis Verhaard
A Reshape operator's input and output tensor point to same data, thus have the same mem area. Change-Id: Ice830f83da78103d54b5f72f5bfc1e6ffa8636c3 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
2020-06-18Further update for MLBEDSW-1872Tim Hall
- Pack and reshape operators were manipulating tensors of different equivalence IDs that refer to the same memory area, causing issues with block dependency checking. Ideally we'd use address overlap calculations for accuracy, but this commit implements a generalised solution by setting memory op IO tensors to use the same equivalence ID. Change-Id: Ia59ae3900f508ffeebaf7af4bca32f5be4e69345 Signed-off-by: Tim Hall <tim.hall@arm.com>
2020-06-18Include 0.180 in HI 1.0Douglas Troha
* Rename debug_addr to debug_address and update page names Change-Id: Ib8d84e6371437439038db411d2f8ff114590878a Signed-off-by: Douglas Troha <douglas.troha@arm.com>
2020-06-18MLBEDSW-2303: Bug fix SplitLouis Verhaard
Usage of the Split operator caused assert failure. Signed-off-by: Louis Verhaard <louis.verhaard@arm.com> Change-Id: Ibe09b9021f768b86731bdc361f9a0875c4379e4b
2020-06-18Add test for len1_array_to_scalar functionDiego Russo
Moved len1_array_to_scalar from a nested function to a staticmethod of TFLiteSubgraph. Change-Id: I182f0b70f03070855c1a4478d26644892c1ebb15 Signed-off-by: Diego Russo <diego.russo@arm.com>
generated by cgit v1.2.1 (git 2.23.0) at 2024-06-01 10:51:56 +0000