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author | Diqing Zhong <diqing.zhong@arm.com> | 2020-04-27 10:27:34 +0200 |
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committer | Tim Hall <tim.hall@arm.com> | 2020-05-13 15:56:19 +0100 |
commit | fed918bfb26dc330a5f066ea5947bc5eb2db4651 (patch) | |
tree | 9200ba8ed1d88789aa74223adb12bb2930c9da2a /ethosu | |
parent | b7311708b81e7022105d335c5e67efcd8f155610 (diff) | |
download | ethos-u-vela-fed918bfb26dc330a5f066ea5947bc5eb2db4651.tar.gz |
Update to HI 0.169
Change-Id: I897bea10ae744162fd285838ee2b2c018695a278
(cherry picked from commit d5ac9b55faa899ac686433e79900cadd321b71bf)
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
Diffstat (limited to 'ethosu')
-rw-r--r-- | ethosu/vela/ethos_u55_regs/ethos_u55_regs.py | 24 | ||||
-rw-r--r-- | ethosu/vela/register_command_stream_generator.py | 8 |
2 files changed, 16 insertions, 16 deletions
diff --git a/ethosu/vela/ethos_u55_regs/ethos_u55_regs.py b/ethosu/vela/ethos_u55_regs/ethos_u55_regs.py index 857f7e43..a3bb0b30 100644 --- a/ethosu/vela/ethos_u55_regs/ethos_u55_regs.py +++ b/ethosu/vela/ethos_u55_regs/ethos_u55_regs.py @@ -19,7 +19,7 @@ from ctypes import * from enum import Enum -ARCH_VER = '0.162.0' +ARCH_VER = '0.169.0' class DEBUG_INTERNAL(Enum): @@ -669,11 +669,11 @@ class elementwise_mode(Enum): SHL = 9 class ifm_precision(Enum): - W8_U8 = 0 - W8_S8 = 1 - W8_U16 = 4 - W8_S16 = 5 - W8_S32 = 9 + U8 = 0 + S8 = 1 + U16 = 4 + S16 = 5 + S32 = 9 class ifm_scale_mode(Enum): SCALE_16BIT = 0 @@ -1958,7 +1958,7 @@ class npu_set_ifm_precision_t(Structure): _fields_ = [ ("cmd_code", c_uint32, 10), ("must_be_zero0", c_uint32, 6), - ("param", c_uint32, 4), + ("precision", c_uint32, 4), ("reserved0", c_uint32, 2), ("format", c_uint32, 2), ("scale_mode", c_uint32, 2), @@ -1970,8 +1970,8 @@ class npu_set_ifm_precision_t(Structure): def set_cmd_code(self, value): cmd_code = value def get_format(self): return format def set_format(self, value): format = value - def get_param(self): return param - def set_param(self, value): param = value + def get_precision(self): return precision + def set_precision(self, value): precision = value def get_round_mode(self): return round_mode def set_round_mode(self, value): round_mode = value def get_scale_mode(self): return scale_mode @@ -2468,7 +2468,7 @@ class npu_set_ifm2_precision_t(Structure): _fields_ = [ ("cmd_code", c_uint32, 10), ("must_be_zero0", c_uint32, 6), - ("param", c_uint32, 4), + ("precision", c_uint32, 4), ("reserved0", c_uint32, 2), ("format", c_uint32, 2), ("reserved1", c_uint32, 8), @@ -2478,8 +2478,8 @@ class npu_set_ifm2_precision_t(Structure): def set_cmd_code(self, value): cmd_code = value def get_format(self): return format def set_format(self, value): format = value - def get_param(self): return param - def set_param(self, value): param = value + def get_precision(self): return precision + def set_precision(self, value): precision = value class npu_set_ifm2_zero_point_t(Structure): _fields_ = [ diff --git a/ethosu/vela/register_command_stream_generator.py b/ethosu/vela/register_command_stream_generator.py index 5563b969..faae2cf3 100644 --- a/ethosu/vela/register_command_stream_generator.py +++ b/ethosu/vela/register_command_stream_generator.py @@ -861,14 +861,14 @@ def generate_register_command_stream(nng, sg, arch, verbose=False): if ifm_dtype.size_in_bits() == 8: if ifm_dtype.type & BaseType.Signed: - prec = ifm_precision.W8_S8 + prec = ifm_precision.S8 else: - prec = ifm_precision.W8_U8 + prec = ifm_precision.U8 elif ifm_dtype.size_in_bits() == 16: if ifm_dtype.type & BaseType.Signed: - prec = ifm_precision.W8_S16 + prec = ifm_precision.S16 else: - prec = ifm_precision.W8_U16 + prec = ifm_precision.U16 ifm_prec = prec.value ifm2_prec = ifm_prec |