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| author | Tim Hall <tim.hall@arm.com> | 2020-08-30 14:40:46 +0100 |
|---|---|---|
| committer | Tim Hall <tim.hall@arm.com> | 2020-08-30 14:42:26 +0100 |
| commit | 749bfd5d2e28dbced80782fcc18cdcd2f9475555 (patch) | |
| tree | fb3b136ba33e0e5b6f13bc6c565617f95c9fa8ed /ethosu/vela/supported_operators.py | |
| parent | 71525176b7aee5ed1dc9f7ae09e11a1884238615 (diff) | |
| download | ethos-u-vela-749bfd5d2e28dbced80782fcc18cdcd2f9475555.tar.gz | |
MLBEDSW-2919: bringup: int16 avgpool diff on FPGA
- Set ACC_FORAMT to 32-bit for pooling operations.
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I69ebd08c2db4c5ec966ca13c872c9b0c8330bb6f
Diffstat (limited to 'ethosu/vela/supported_operators.py')
0 files changed, 0 insertions, 0 deletions