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author | Tim Hall <tim.hall@arm.com> | 2022-09-02 15:01:01 +0100 |
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committer | tim.hall <tim.hall@arm.com> | 2022-09-08 13:42:57 +0000 |
commit | d6efcd3cdcd8295fbbe7dd47a7074be39eaf03e4 (patch) | |
tree | 85e98d9d29fb087a9faceb385566f551e2c988dd /ethosu/vela/register_command_stream_generator.py | |
parent | 66591653b7eb465e041507049bce3fb3e02a7d29 (diff) | |
download | ethos-u-vela-d6efcd3cdcd8295fbbe7dd47a7074be39eaf03e4.tar.gz |
MLEMBED-1918: Issue with REDUCE_SUM on Ethos-U65-5123.6.0.rc0
- Ethos-U65-512 requires the input to REDUCE_SUM to use NHWC format
- Updated the graph optimiser format check to cover this condition
- Added a exception check to the backend of the compiler to verify that
this condition is not been violated by the external api or Vela internals
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I2f1fabcbd264daf77d5822349d855a3a32b12c64
Diffstat (limited to 'ethosu/vela/register_command_stream_generator.py')
-rw-r--r-- | ethosu/vela/register_command_stream_generator.py | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/ethosu/vela/register_command_stream_generator.py b/ethosu/vela/register_command_stream_generator.py index a8d1ddff..5680c96f 100644 --- a/ethosu/vela/register_command_stream_generator.py +++ b/ethosu/vela/register_command_stream_generator.py @@ -931,6 +931,19 @@ def generate_conv_depthwise_op( def generate_pooling_op(emit: CommandStreamEmitter, npu_op: NpuPoolingOperation, arch: ArchitectureFeatures): """Generates register commands for pooling operations""" + # check that reduce_sum input is NHWC + if npu_op.sub_op_type == NpuPoolingOp.REDUCE_SUM and npu_op.ifm.layout != NpuLayout.NHWC: + if npu_op.ifm.data_type == NpuDataType.INT32: + raise VelaError( + f"REDUCE_SUM ({npu_op.name}) with IFM data type of INT32 requires IFM layout to be NHWC" + f" ({npu_op.ifm.name} == {npu_op.ifm.layout})" + ) + elif arch.accelerator_config == Accelerator.Ethos_U65_512: + raise VelaError( + f"REDUCE_SUM ({npu_op.name}) with accelerator config of Ethos_U65_512 requires IFM layout to be NHWC" + f" ({npu_op.ifm.name} == {npu_op.ifm.layout})" + ) + use_global_scale = ( npu_op.sub_op_type in (NpuPoolingOp.AVERAGE, NpuPoolingOp.REDUCE_SUM) and sum(npu_op.padding) == 0 ) |