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author | Andreas Nevalainen <andreas.nevalainen@arm.com> | 2020-10-28 15:42:08 +0100 |
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committer | patrik.gustavsson <patrik.gustavsson@arm.com> | 2020-11-11 08:34:16 +0000 |
commit | 897cc14968e017b1f48f376f7f7cefc515c5fe88 (patch) | |
tree | 27d17a59f1529c1ed0b1cc59e60438ee7f5d29d2 /ethosu/vela/high_level_command_stream.py | |
parent | 73320a48dfa711f5938b0e3d8e03b9858558b899 (diff) | |
download | ethos-u-vela-897cc14968e017b1f48f376f7f7cefc515c5fe88.tar.gz |
MLBEDSW-3222: Bias tensors in fast storage
For IFM streamed cascades bias tensors are read several times.
Moves these tensors to fast storage and add DMA commands.
Change-Id: I630f6275986c1b5e3f126c925b11e22500fb1128
Signed-off-by: Andreas Nevalainen <andreas.nevalainen@arm.com>
Diffstat (limited to 'ethosu/vela/high_level_command_stream.py')
-rw-r--r-- | ethosu/vela/high_level_command_stream.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/ethosu/vela/high_level_command_stream.py b/ethosu/vela/high_level_command_stream.py index b8a19f50..a5372d73 100644 --- a/ethosu/vela/high_level_command_stream.py +++ b/ethosu/vela/high_level_command_stream.py @@ -21,6 +21,7 @@ import numpy as np from .numeric_util import round_up_divide from .operation import NpuBlockType +from .operation import Op from .range_set import AccessDirection from .range_set import MemoryAccessSet from .range_set import MemoryRangeSet @@ -236,6 +237,11 @@ class NpuStripe(Command): ), AccessDirection.Read, ) + if self.scale_tensor is not None and self.scale_tensor.ops[0].type == Op.DMA: + res.add( + self.scale_tensor.get_address_ranges_for_coordinates([0], self.scale_tensor.shape), + AccessDirection.Read, + ) # Add read access to SHRAM by any LUT-s for tens in self.ps.intermediates: if tens.purpose == TensorPurpose.LUT and tens.mem_area == MemArea.Shram: |