aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorTim Hall <tim.hall@arm.com>2020-08-30 14:40:46 +0100
committerTim Hall <tim.hall@arm.com>2020-08-30 14:42:26 +0100
commit749bfd5d2e28dbced80782fcc18cdcd2f9475555 (patch)
treefb3b136ba33e0e5b6f13bc6c565617f95c9fa8ed
parent71525176b7aee5ed1dc9f7ae09e11a1884238615 (diff)
downloadethos-u-vela-749bfd5d2e28dbced80782fcc18cdcd2f9475555.tar.gz
MLBEDSW-2919: bringup: int16 avgpool diff on FPGA
- Set ACC_FORAMT to 32-bit for pooling operations. Signed-off-by: Tim Hall <tim.hall@arm.com> Change-Id: I69ebd08c2db4c5ec966ca13c872c9b0c8330bb6f
-rw-r--r--ethosu/vela/shared_buffer_allocation.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/ethosu/vela/shared_buffer_allocation.py b/ethosu/vela/shared_buffer_allocation.py
index fdcbe94a..0f5c1c81 100644
--- a/ethosu/vela/shared_buffer_allocation.py
+++ b/ethosu/vela/shared_buffer_allocation.py
@@ -84,7 +84,8 @@ class SharedBufferAllocation:
else:
self.ifm_depth = ifm_tensor.shape[-1]
if self.ifm_bits == 16:
- self.use_accumulator_element = SHRAMElements.Acc40
+ if ps.npu_block_type != NpuBlockType.Pooling:
+ self.use_accumulator_element = SHRAMElements.Acc40
self.use_ifm_element = self.use_ifm_element + 1
assert (self.use_ifm_element == SHRAMElements.IFM16) or (
self.use_ifm_element == SHRAMElements.IFM16_Elementwise