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author | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2022-06-28 11:27:07 +0200 |
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committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2022-06-29 12:09:52 +0200 |
commit | 3706043e9586c7c3a11ed9592bfaeb5ac9d2a27c (patch) | |
tree | ec645e76d20929d92a2afee69a025ffda2b3bfa0 /kernel/ethosu_core_interface.h | |
parent | 087ea21ebad72c0b5563f04370abc3c6cc9ce8ad (diff) | |
download | ethos-u-linux-driver-stack-3706043e9586c7c3a11ed9592bfaeb5ac9d2a27c.tar.gz |
Add missing padding to core interface
The padding is important to separate the read- and write indices by
at least one cache line, to prevent cache clean and invalidation to
corrupt data for the remote CPU.
Change-Id: I1d50ac6c63ef4cb3e11b0c293aefaac34ac8eb1f
Diffstat (limited to 'kernel/ethosu_core_interface.h')
-rw-r--r-- | kernel/ethosu_core_interface.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/kernel/ethosu_core_interface.h b/kernel/ethosu_core_interface.h index 057e3c2..193b296 100644 --- a/kernel/ethosu_core_interface.h +++ b/kernel/ethosu_core_interface.h @@ -75,10 +75,19 @@ struct ethosu_core_msg { /** * struct ethosu_core_queue_header - Message queue header + * + * The read and write indices must be separated by at least one cache line, + * else updating the read index would also overwrite the write index when + * the cache line is flushed. Because of this the message queues should be + * placed on cache line aligned addresses. + * + * The cache line length for Cortex-M is typically fixed at 32 bytes. The + * kernel driver is setup to allocated non cached memory. */ struct ethosu_core_queue_header { uint32_t size; uint32_t read; + uint32_t pad[6]; uint32_t write; }; |