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#! cpp
/*
* Copyright (c) 2019-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef STACK_SIZE
#define STACK_SIZE 0x8000
#endif
#ifndef HEAP_SIZE
#define HEAP_SIZE 0x8000
#endif
APP_IMAGE 0x00000000 0x01000000
{
; ITCM 512kB
rom_exec 0x00000000 0x00080000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Shared between Cortex-M and the NPU
DATA_SRAM 0x01000000 UNINIT 0x00200000 {}
; SSE-300 SRAM (3 cycles read latency) from M55/U55
; 2x2MB - only first part mapped
SRAM 0x21000000 UNINIT 0x00200000
{
#ifndef ETHOSU_FAST_MEMORY_SIZE
; Place tensor arena in SRAM if we do not have a fast memory area
* (.bss.NoInit) ; Tensor Arena
#else
* (.bss.ethosu_scratch)
#endif
}
; DTCM 512kB
; Only accessible from the Cortex-M
DTCM 0x20000000 (0x00080000 - STACK_SIZE - HEAP_SIZE)
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP (0x20080000 - STACK_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {}
ARM_LIB_STACK (0x20080000 - STACK_SIZE) EMPTY ALIGN 8 STACK_SIZE {}
}
LOAD_REGION_1 0x60000000 0x02000000
{
; 2GB DDR4 available
rom_dram 0x60000000 0x02000000
{
* (network_model_sec)
* (input_data_sec)
* (expected_output_data_sec)
}
#ifdef ETHOSU_FAST_MEMORY_SIZE
; Place tensor arena in DRAM if we have a fast memory area
ARENA +0 UNINIT ALIGN 16
{
* (.bss.NoInit) ; Tensor Arena
}
#endif
}
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