/* * Copyright (c) 2019-2022 Arm Limited. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* * This is a simplified picture of the Corstone-300 memory system. * Please refer to the Corstone SSE-300 Technical Reference Manual for * further information. * * https://developer.arm.com/ip-products/subsystem/corstone/corstone-300 * * +---------------+ +---------------+ +------+ * | Ethos-U55 | | Cortex-M55 +--+ ITCM | * | | | | +------+ * | | | | * | | | | +------+ * | M1 M0 | | +--+ DTCM | * +---+-------+---+ +-------+-------+ +------+ * | | | * | +---+---------------+-----+ * | | AMBA AXI NIC-400-Lite | * | +---+-----------------+---+ * | | | * +---+-------+------------+ +--+-------+ * | AMBA AXI NIC-400 | | SSE-300 | * +---+--------+--------+--+ | SRAM | * | | | +----------+ * +---+---+ +--+---+ +--+--+ * | Flash | | BRAM | | DDR | * +-------+ +------+ +-----+ * * +-----------------------+-------------+-------------+----+--------------------------------------+ * | Memory region name | Base addr | Size |IDAU| MCC load address + remarks | * +-----------------------+-------------+-------------+----+--------------------------------------+ * | ITCM | 0x0000_0000 | 0x0008_0000 | NS | 0x0000_0000; 512 kiB | * | ITCM | 0x1000_0000 | 0x0008_0000 | S | Secure alias for NS ITCM | * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0010_0000 | NS | 0x0100_0000; 1 MiB | * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0010_0000 | S | Secure alias for NS BRAM | * | DTCM | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each | * | DTCM | 0x3000_0000 | 0x0008_0000 | S | Secure alias for NS DTCM | * | SSE-300 internal SRAM | 0x2100_0000 | 0x0020_0000 | NS | 1 bank of 2 MiB; 3cc latency) | * | SSE-300 internal SRAM | 0x3100_0000 | 0x0020_0000 | S | Secure alias for NS internal SRAM | * | QSPI external flash | 0x2800_0000 | 0x0080_0000 | NS | 8MB | * | QSPI external flash | 0x3800_0000 | 0x0080_0000 | S | 8MB | * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank | * | DDR | 0x7000_0000 | 0x1000_0000 | S | 0x0C00_0000; 256 MiB bank | * +-----------------------+-------------+-------------+----+--------------------------------------+ * * Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and * the model should only be placed in those regions. * * Note: Alias regions means that secure and non-secure addresses are mapped to the same physical * memory banks. */ #ifndef ETHOSU_MODEL /* default value - '1', for DRAM */ #define ETHOSU_MODEL 1 #endif #ifndef ETHOSU_ARENA /* default value - '1', for DRAM */ #define ETHOSU_ARENA 1 #endif #ifndef STACK_SIZE #define STACK_SIZE 0x8000 #endif #ifndef HEAP_SIZE #define HEAP_SIZE 0x10000 #endif #if defined(TRUSTZONE_BUILD) && !defined(ETHOSU_TEST) /* * Include trustzone.h with common addresses and sizes. * The build configuration sets whether TRUSTZONE_SECURE is set or * TRUSTZONE_NONSECURE which sets the memory start addresses and sizes. */ #include "trustzone.h" #define USE_TRUSTZONE #else //TRUSTZONE_BUILD #define LR_START 0x10000000 #define LR_SIZE 0x00080000 #define ITCM_START 0x10000000 #define ITCM_SIZE 0x00080000 #define BRAM_START 0x11000000 #define BRAM_SIZE 0x00100000 #define DTCM_START 0x30000000 #define DTCM_SIZE 0x00080000 #define SRAM_START 0x31000000 #define SRAM_SIZE 0x00200000 #define QSPI_START 0x38000000 #define QSPI_SIZE 0x00800000 #define DDR_START 0x70000000 #define DDR_SIZE 0x02000000 #define STACK_HEAP 0x30080000 #endif //TRUSTZONE_BUILD /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif APP_IMAGE LR_START LR_SIZE { ; ITCM 512kB rom_exec ITCM_START ITCM_SIZE { *.o (RESET, +First) * (InRoot$$Sections, .init_array*, .ARM*) ; Make sure reset_handler ends up in root segment, when split across ; ITCM and DTCM startup_ARMCM55.o .ANY2 (+RO) } ; DTCM 512kB ; Only accessible from the Cortex-M DTCM DTCM_START (DTCM_SIZE - STACK_SIZE - HEAP_SIZE - __STACKSEAL_SIZE) { .ANY1 (+RW +ZI) } ARM_LIB_HEAP (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {} ARM_LIB_STACK (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE) EMPTY ALIGN 8 STACK_SIZE {} #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } LOAD_REGION_BRAM BRAM_START BRAM_SIZE { #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) ; MPS3 BRAM ; Shared between Cortex-M and the NPU BRAM BRAM_START (BRAM_SIZE - TZ_NSC_SIZE) { * (.sram.data) } ROM_NSC TZ_NSC_START TZ_NSC_SIZE { *(Veneer$$CMSE) } #else ; MPS3 BRAM BRAM BRAM_START BRAM_SIZE { * (.sram.data) } #endif TEXT1 +0 { ; Code segment is placed with higher priority (.ANY2) in ITCM. If ITCM gets ; full, then the remaining symbols may be placed here in BRAM. .ANY1 (+RO) } } LOAD_REGION_SRAM SRAM_START SRAM_SIZE { ; 2MB SSE-300 SRAM (3 cycles read latency) from M55/U55 SRAM SRAM_START SRAM_SIZE { #if (ETHOSU_MODEL == 0) ; Place network model in SRAM * (network_model_sec) #endif #if (ETHOSU_ARENA == 0) ; Place tensor arena in SRAM * (.bss.tensor_arena) #endif ; Place scratch buffer in SRAM * (.bss.ethosu_scratch) } } LOAD_REGION_1 DDR_START DDR_SIZE { ; 2GB DDR4 available rom_dram DDR_START #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_NONSECURE) { } #else //trustzone secure or non-trustzone ; Place model and its affiliates in DRAM { #if (ETHOSU_MODEL == 1) * (network_model_sec) #endif * (input_data_sec) * (expected_output_data_sec) * (output_data_sec) * (sec_command_stream, sec_weight_data, sec_input_data) * (ethosu_core_in_queue) * (ethosu_core_out_queue) } #if (ETHOSU_ARENA == 1) ; Place tensor arena in DRAM if we have a fast memory area ARENA +0 UNINIT ALIGN 16 { * (.bss.tensor_arena) } #endif #endif }