From 4756bf12f9dbe6502b3831808d7e4f217586980a Mon Sep 17 00:00:00 2001 From: Nir Ekhauz Date: Sun, 27 Jun 2021 11:20:24 +0300 Subject: run_platform.py PMU configuration Enable configuration of up to 4 PMU counters Jira: MLBEDSW-4744 Change-Id: I08e9073d827033b3340bffd680288b1a83833d64 --- targets/corstone-300/CMakeLists.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'targets/corstone-300') diff --git a/targets/corstone-300/CMakeLists.txt b/targets/corstone-300/CMakeLists.txt index 9c527fc..06469d8 100644 --- a/targets/corstone-300/CMakeLists.txt +++ b/targets/corstone-300/CMakeLists.txt @@ -58,6 +58,17 @@ set(ETHOSU_TARGET_NPU_CONFIG "ethos-u55-128" CACHE STRING "NPU configuration") set(ETHOSU_TARGET_NPU_COUNT 1 CACHE INTERNAL "Number of NPUs") set(ETHOSU_TARGET_NPU_TA_COUNT 2 CACHE INTERNAL "Number of timing adapters per NPU") +set(ETHOSU_PMU_EVENT_0 0 CACHE STRING "PMU Event #0") +set(ETHOSU_PMU_EVENT_1 0 CACHE STRING "PMU Event #1") +set(ETHOSU_PMU_EVENT_2 0 CACHE STRING "PMU Event #2") +set(ETHOSU_PMU_EVENT_3 0 CACHE STRING "PMU Event #3") + +target_compile_definitions(ethosu_target_common INTERFACE + ETHOSU_PMU_EVENT_0=${ETHOSU_PMU_EVENT_0} + ETHOSU_PMU_EVENT_1=${ETHOSU_PMU_EVENT_1} + ETHOSU_PMU_EVENT_2=${ETHOSU_PMU_EVENT_2} + ETHOSU_PMU_EVENT_3=${ETHOSU_PMU_EVENT_3}) + target_compile_definitions(ethosu_target_common INTERFACE ETHOSU_NPU_TA_COUNT=${ETHOSU_TARGET_NPU_TA_COUNT} ETHOSU_NPU_COUNT=${ETHOSU_TARGET_NPU_COUNT}) -- cgit v1.2.1