From 3c505caf6632619df297d4448fc68e987849f6c6 Mon Sep 17 00:00:00 2001 From: Nir Ekhauz Date: Sun, 6 Jun 2021 14:57:50 +0300 Subject: Add memory area to run_platform.py Control the placement of the model and the arena for baremetal application in SRAM/DRAM by 4 configurable options: a. Model in SRAM and Arena in SRAM b. Model in SRAM and Arena in DRAM c. Model in DRAM and Arena in DRAM w/o Scratch buffer d. Model in DRAM and Arena in DRAM with Scratch buffer in SRAM Change-Id: Ia154be8a1c88cb13aeee62e701c2db7719a9d71c --- targets/corstone-300/platform.ld | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) (limited to 'targets/corstone-300/platform.ld') diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld index 8d44c1b..ec58acc 100644 --- a/targets/corstone-300/platform.ld +++ b/targets/corstone-300/platform.ld @@ -65,6 +65,16 @@ * memory banks. */ +#ifndef ETHOSU_MODEL + /* default value - '1', for DRAM */ + #define ETHOSU_MODEL 1 +#endif + +#ifndef ETHOSU_ARENA + /* default value - '1', for DRAM */ + #define ETHOSU_ARENA 1 +#endif + __STACK_SIZE = 0x00008000; __HEAP_SIZE = 0x00008000; @@ -239,25 +249,32 @@ SECTIONS .sram.bss : { . = ALIGN(16); -#ifdef ETHOSU_FAST_MEMORY_SIZE - *(.bss.ethosu_scratch); -#else +#if (ETHOSU_MODEL == 0) + * (network_model_sec) +#endif + +#if (ETHOSU_ARENA == 0) *(.bss.tensor_arena) #endif + + *(.bss.ethosu_scratch); *.(output_data_sec) } > SRAM :null .ddr : { -#ifdef ETHOSU_FAST_MEMORY_SIZE +#if (ETHOSU_ARENA == 1) . = ALIGN(16); *(.bss.tensor_arena) #endif + . = ALIGN(4); *(input_data_sec) . = ALIGN(16); +#if (ETHOSU_MODEL == 1) *(network_model_sec) - *(expected_output_data_sec) +#endif + * (expected_output_data_sec) } > DDR :rom_dram __eddr_data = ALIGN (16) ; -- cgit v1.2.1