From 991af2bd8fb6c79dfb317837353857f34a727b17 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonny=20Sv=C3=A4rd?= <jonny.svaerd@arm.com>
Date: Thu, 15 Apr 2021 17:31:01 +0200
Subject: Enable MPU and CPU cache for Corstone-300

- Enable CPU instruction- and data cache by default.
- Add a CMake option to turn CPU cache on/off.

- Add basic MPU configuration for memory areas. Make the code
  segment RO (NS address' are reachable from secure state,
  hence MPU config entries for both S and NS address of ITCM).

- Target latest NPU API version
Change-Id: Ie9bf2f02e5ad534375d146804fdc66b9f2f6770f

Change-Id: I9def430d1e61d18e521798db4f48ed0a8c58380e
---
 targets/corstone-300/mpu.hpp | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 targets/corstone-300/mpu.hpp

(limited to 'targets/corstone-300/mpu.hpp')

diff --git a/targets/corstone-300/mpu.hpp b/targets/corstone-300/mpu.hpp
new file mode 100644
index 0000000..dff73b6
--- /dev/null
+++ b/targets/corstone-300/mpu.hpp
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/****************************************************************************
+ * Includes
+ ****************************************************************************/
+
+#include <cstdint>
+
+/****************************************************************************
+ * Types and functions
+ ****************************************************************************/
+
+namespace EthosU {
+namespace Mpu {
+
+enum { WTRA_index, WBWARA_index };
+
+/**
+ * Dump the MPU tables.
+ */
+void dump();
+
+void loadAndEnableConfig(ARM_MPU_Region_t const *table, uint32_t cnt);
+
+}; // namespace Mpu
+}; // namespace EthosU
-- 
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