From 991af2bd8fb6c79dfb317837353857f34a727b17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonny=20Sv=C3=A4rd?= Date: Thu, 15 Apr 2021 17:31:01 +0200 Subject: Enable MPU and CPU cache for Corstone-300 - Enable CPU instruction- and data cache by default. - Add a CMake option to turn CPU cache on/off. - Add basic MPU configuration for memory areas. Make the code segment RO (NS address' are reachable from secure state, hence MPU config entries for both S and NS address of ITCM). - Target latest NPU API version Change-Id: Ie9bf2f02e5ad534375d146804fdc66b9f2f6770f Change-Id: I9def430d1e61d18e521798db4f48ed0a8c58380e --- targets/corstone-300/CMakeLists.txt | 10 ++++- targets/corstone-300/mpu.cpp | 79 ++++++++++++++++++++++++++++++++++ targets/corstone-300/mpu.hpp | 42 ++++++++++++++++++ targets/corstone-300/target.cpp | 85 ++++++++++++++++++++++++++++++++++++- 4 files changed, 213 insertions(+), 3 deletions(-) create mode 100644 targets/corstone-300/mpu.cpp create mode 100644 targets/corstone-300/mpu.hpp diff --git a/targets/corstone-300/CMakeLists.txt b/targets/corstone-300/CMakeLists.txt index 538a978..e791cfd 100644 --- a/targets/corstone-300/CMakeLists.txt +++ b/targets/corstone-300/CMakeLists.txt @@ -28,6 +28,8 @@ endif() set(ETHOSU_COMMAND_DEFAULT ${CMAKE_CURRENT_SOURCE_DIR}/../../scripts/run_ctest.py -t corstone-300) +option(CPU_CACHE_ENABLE "Enable CPU instruction- and data cache" ON) + ############################################################################# # Project ############################################################################# @@ -59,6 +61,11 @@ target_compile_definitions(ethosu_target_common INTERFACE ETHOSU_NPU_TA_COUNT=${ETHOSU_TARGET_NPU_TA_COUNT} ETHOSU_NPU_COUNT=${ETHOSU_TARGET_NPU_COUNT}) +if (CPU_CACHE_ENABLE) + target_compile_definitions(ethosu_target_common INTERFACE + CPU_CACHE_ENABLE) +endif() + # Linker script ethosu_target_link_options(ethosu_target_link INTERFACE LINK_FILE platform @@ -68,7 +75,8 @@ ethosu_target_link_options(ethosu_target_link INTERFACE target_sources(ethosu_target_startup INTERFACE retarget.c uart.c - target.cpp) + target.cpp + mpu.cpp) target_compile_definitions(ethosu_core_driver PUBLIC ETHOSU) target_link_libraries(ethosu_target_startup INTERFACE ethosu_core_driver timing_adapter) diff --git a/targets/corstone-300/mpu.cpp b/targets/corstone-300/mpu.cpp new file mode 100644 index 0000000..645723c --- /dev/null +++ b/targets/corstone-300/mpu.cpp @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/**************************************************************************** + * Includes + ****************************************************************************/ + +#include "mpu.hpp" + +#include +#include +#include + +using namespace std; + +/**************************************************************************** + * Functions + ****************************************************************************/ + +namespace EthosU { +namespace Mpu { + +void dump() { +#ifdef ARM_MPU_ARMV8_H + uint32_t mpuRegions = (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; + + printf("MPU available with " PRIu32 " regions.\n", mpuRegions); + + printf(" PRIVDEFENA : %lx\n", (MPU->CTRL & MPU_CTRL_PRIVDEFENA_Msk) >> MPU_CTRL_PRIVDEFENA_Pos); + printf(" HFNMIENA : %lx\n", (MPU->CTRL & MPU_CTRL_HFNMIENA_Msk) >> MPU_CTRL_HFNMIENA_Pos); + printf(" ENABLE : %lx\n", (MPU->CTRL & MPU_CTRL_ENABLE_Msk) >> MPU_CTRL_ENABLE_Pos); + + for (size_t region = 0; region < mpuRegions; region++) { + MPU->RNR = region; + printf("-- Region %2d - RBAR:%08" PRIx32 " RLAR:%08" PRIx32 "\n", region, MPU->RBAR, MPU->RLAR); + } +#endif +} + +static void initializeAttributes() { +#ifdef ARM_MPU_ARMV8_H + /* Initialize attributes corresponding to the enums defined in mpu.hpp */ + const uint8_t WTRA = + ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0); // Non-transient, Write-Through, Read-allocate, Not Write-allocate + const uint8_t WBWARA = ARM_MPU_ATTR_MEMORY_(1, 1, 1, 1); // Non-transient, Write-Back, Read-allocate, Write-allocate + + ARM_MPU_SetMemAttr(WTRA_index, ARM_MPU_ATTR(WTRA, WTRA)); + ARM_MPU_SetMemAttr(WBWARA_index, ARM_MPU_ATTR(WBWARA, WBWARA)); +#endif +} + +void loadAndEnableConfig(ARM_MPU_Region_t const *table, uint32_t cnt) { +#ifdef ARM_MPU_ARMV8_H + initializeAttributes(); + + ARM_MPU_Load(0, table, cnt); + + // Enable MPU with default priv access to all other regions + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); +#endif +} + +}; // namespace Mpu +}; // namespace EthosU diff --git a/targets/corstone-300/mpu.hpp b/targets/corstone-300/mpu.hpp new file mode 100644 index 0000000..dff73b6 --- /dev/null +++ b/targets/corstone-300/mpu.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/**************************************************************************** + * Includes + ****************************************************************************/ + +#include + +/**************************************************************************** + * Types and functions + ****************************************************************************/ + +namespace EthosU { +namespace Mpu { + +enum { WTRA_index, WBWARA_index }; + +/** + * Dump the MPU tables. + */ +void dump(); + +void loadAndEnableConfig(ARM_MPU_Region_t const *table, uint32_t cnt); + +}; // namespace Mpu +}; // namespace EthosU diff --git a/targets/corstone-300/target.cpp b/targets/corstone-300/target.cpp index e5f4680..a44c12f 100644 --- a/targets/corstone-300/target.cpp +++ b/targets/corstone-300/target.cpp @@ -26,6 +26,7 @@ #include #endif +#include "mpu.hpp" #include #include "uart.h" @@ -33,6 +34,7 @@ #include #include #include +#include using namespace EthosU; @@ -57,6 +59,10 @@ __attribute__((aligned(16), section(".bss.ethosu_scratch"))) uint8_t ethosu_scra #define ETHOSU_FAST_MEMORY_SIZE 0 #endif +#ifdef ETHOSU +struct ethosu_driver *ethosu0_driver = ðosu_drv; +#endif + static uintptr_t ethosu_ta_base_addrs[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT] = { {ETHOSU0_TA0_BASE_ADDRESS, ETHOSU0_TA1_BASE_ADDRESS}}; struct timing_adapter ethosu_ta[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT]; @@ -152,15 +158,90 @@ void targetSetup() { #ifdef ETHOSU // Initialize Ethos-U NPU driver - if (ethosu_init_v3(reinterpret_cast(ETHOSU_BASE_ADDRESS), ethosu_scratch, ETHOSU_FAST_MEMORY_SIZE, 1, 1)) { + if (ethosu_init_v4(ethosu0_driver, + reinterpret_cast(ETHOSU_BASE_ADDRESS), + ethosu_scratch, + ETHOSU_FAST_MEMORY_SIZE, + 1, + 1)) { printf("Failed to initialize NPU.\n"); return; } - /* Assumes SCB->VTOR point to RW memory */ + // Assumes SCB->VTOR point to RW memory NVIC_SetVector(static_cast(ETHOSU_IRQ), (uint32_t)ðosuIrqHandler); NVIC_EnableIRQ(static_cast(ETHOSU_IRQ)); #endif + + // MPU setup + const std::vector mpuConfig = { + { + // ITCM + ARM_MPU_RBAR(0x00000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 1, // Read-Only + 1, // Non-Privileged + 0), // eXecute Never disabled + ARM_MPU_RLAR(0x0007ffff, // Limit + Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate + }, + { + // ITCM + ARM_MPU_RBAR(0x10000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 1, // Read-Only + 1, // Non-Privileged + 0), // eXecute Never disabled + ARM_MPU_RLAR(0x1007ffff, // Limit + Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate + }, + { + // FPGA DATA SRAM; BRAM + ARM_MPU_RBAR(0x11000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 0), // eXecute Never disabled + ARM_MPU_RLAR(0x111fffff, // Limit + Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + }, + { + // DTCM + ARM_MPU_RBAR(0x30000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 1), // eXecute Never enabled + ARM_MPU_RLAR(0x3007ffff, // Limit + Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + }, + { + // SSE-300 internal SRAM + ARM_MPU_RBAR(0x31000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 1), // eXecute Never enabled + ARM_MPU_RLAR(0x313fffff, // Limit + Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + }, + { + ARM_MPU_RBAR(0x70000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 1), // eXecute Never enabled + ARM_MPU_RLAR(0x7fffffff, // Limit + Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + }}; + + // Setup MPU configuration + Mpu::loadAndEnableConfig(&mpuConfig[0], mpuConfig.size()); + +#if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + SCB_EnableICache(); + SCB_EnableDCache(); +#endif } } // namespace EthosU -- cgit v1.2.1