From 3adfbc1bf472a095ef01e9f62f80d55e0d834dfe Mon Sep 17 00:00:00 2001
From: Nir Ekhauz <nir.ekhauz@arm.com>
Date: Mon, 24 May 2021 13:16:52 +0300
Subject: Corstone-300 reduced SRAM size

Fix inconsistencies between the scatter file and linker script

Jira: MLBEDSW-4596
Change-Id: I4d31fc89ef0d0371e1ba8758d60871674cf844a9
---
 targets/corstone-300/platform.ld      | 54 +++++++++++++++++++++++++++++++++--
 targets/corstone-300/platform.scatter |  7 ++---
 2 files changed, 55 insertions(+), 6 deletions(-)

diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld
index bcda98c..8d44c1b 100644
--- a/targets/corstone-300/platform.ld
+++ b/targets/corstone-300/platform.ld
@@ -16,14 +16,64 @@
  * limitations under the License.
  */
 
+ /*
+ * This is a simplified picture of the Corstone-300 memory system.
+ * Please refer to the Corstone SSE-300 Technical Reference Manual for
+ * further information.
+ *
+ * https://developer.arm.com/ip-products/subsystem/corstone/corstone-300
+ *
+ * +---------------+   +---------------+  +------+
+ * | Ethos-U55     |   | Cortex-M55    +--+ ITCM |
+ * |               |   |               |  +------+
+ * |               |   |               |
+ * |               |   |               |  +------+
+ * |  M1      M0   |   |               +--+ DTCM |
+ * +---+-------+---+   +-------+-------+  +------+
+ *     |       |               |
+ *     |   +---+---------------+-----+
+ *     |   | AMBA AXI NIC-400-Lite   |
+ *     |   +---+-----------------+---+
+ *     |       |                 |
+ * +---+-------+------------+ +--+-------+
+ * | AMBA AXI NIC-400       | | SSE-300  |
+ * +---+--------+--------+--+ | SRAM     |
+ *     |        |        |    +----------+
+ * +---+---+ +--+---+ +--+--+
+ * | Flash | | BRAM | | DDR |
+ * +-------+ +------+ +-----+
+ *
+ * +-----------------------+-------------+-------------+----+--------------------------------------+
+ * |  Memory region name   | Base addr   |    Size     |IDAU|  MCC load address + remarks          |
+ * +-----------------------+-------------+-------------+----+--------------------------------------+
+ * | ITCM                  | 0x0000_0000 | 0x0008_0000 | NS | 0x0000_0000; 512 kiB                 |
+ * | ITCM                  | 0x1000_0000 | 0x0008_0000 | S  | Secure alias for NS ITCM             |
+ * | FPGA Data SRAM; BRAM  | 0x0100_0000 | 0x0040_0000 | NS | 0x0040_0000; 2 MiB                   |
+ * | FPGA data SRAM; BRAM  | 0x1100_0000 | 0x0040_0000 | S  | Secure alias for NS BRAM             |
+ * | DTCM                  | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each        |
+ * | DTCM                  | 0x3000_0000 | 0x0008_0000 | S  | Secure alias for NS DTCM             |
+ * | SSE-300 internal SRAM | 0x2100_0000 | 0x0020_0000 | NS | 1 bank of 2 MiB; 3cc latency)        |
+ * | SSE-300 internal SRAM | 0x3100_0000 | 0x0020_0000 | S  | Secure alias for NS internal SRAM    |
+ * | DDR                   | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank            |
+ * | DDR                   | 0x7000_0000 | 0x1000_0000 | S  | 0x0C00_0000; 256 MiB bank            |
+ * +-----------------------+-------------+-------------+----+--------------------------------------+
+ *
+ *  Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and
+ *        the model should only be placed in those regions.
+ *
+ *  Note: Alias regions means that secure and non-secure addresses are mapped to the same physical
+ *        memory banks.
+ */
+
 __STACK_SIZE = 0x00008000;
 __HEAP_SIZE  = 0x00008000;
 
 MEMORY
 {
   ITCM  (rx)  : ORIGIN = 0x10000000, LENGTH = 0x00080000
-  SRAM  (rw)  : ORIGIN = 0x11000000, LENGTH = 0x01000000
+  BRAM  (rw)  : ORIGIN = 0x11000000, LENGTH = 0x00400000
   DTCM  (rw)  : ORIGIN = 0x30000000, LENGTH = 0x00080000
+  SRAM  (rw)  : ORIGIN = 0x31000000, LENGTH = 0x00200000
   DDR   (rwx) : ORIGIN = 0x70000000, LENGTH = 0x60000000
 }
 
@@ -215,7 +265,7 @@ SECTIONS
     __sram_data_start__ = .;
     *(.sram.data)
     __sram_data_end__ = .;
-  } > SRAM AT >DDR :rom_dram
+  } > BRAM AT >DDR :rom_dram
 
   .bss :
   {
diff --git a/targets/corstone-300/platform.scatter b/targets/corstone-300/platform.scatter
index fe63d01..bf143dc 100644
--- a/targets/corstone-300/platform.scatter
+++ b/targets/corstone-300/platform.scatter
@@ -54,8 +54,8 @@
  * | FPGA data SRAM; BRAM  | 0x1100_0000 | 0x0020_0000 | S  | Secure alias for NS BRAM             |
  * | DTCM                  | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each        |
  * | DTCM                  | 0x3000_0000 | 0x0008_0000 | S  | Secure alias for NS DTCM             |
- * | SSE-300 internal SRAM | 0x2100_0000 | 0x0040_0000 | NS | 2 banks of 2 MiB each; 3cc latency)  |
- * | SSE-300 internal SRAM | 0x3100_0000 | 0x0040_0000 | S  | Secure alias for NS internal SRAM    |
+ * | SSE-300 internal SRAM | 0x2100_0000 | 0x0020_0000 | NS | 1 bank of 2 MiB; 3cc latency)        |
+ * | SSE-300 internal SRAM | 0x3100_0000 | 0x0020_0000 | S  | Secure alias for NS internal SRAM    |
  * | DDR                   | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank            |
  * | DDR                   | 0x7000_0000 | 0x1000_0000 | S  | 0x0C00_0000; 256 MiB bank            |
  * +-----------------------+-------------+-------------+----+--------------------------------------+
@@ -158,8 +158,7 @@ APP_IMAGE LR_START LR_SIZE
         .ANY1 (+RW +ZI)
     }
 
-    ; SSE-300 SRAM (3 cycles read latency) from M55/U55
-    ; 2x2MB - only first part mapped
+    ; 2MB SSE-300 SRAM (3 cycles read latency) from M55/U55
     SRAM SRAM_START UNINIT SRAM_SIZE
     {
 #ifndef ETHOSU_FAST_MEMORY_SIZE
-- 
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