diff options
| -rw-r--r-- | targets/corstone-300/platform.ld | 178 |
1 files changed, 44 insertions, 134 deletions
diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld index 091a117..bcda98c 100644 --- a/targets/corstone-300/platform.ld +++ b/targets/corstone-300/platform.ld @@ -16,75 +16,22 @@ * limitations under the License. */ -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- ITCM Configuration ---------------------------------- - <h> Flash Configuration - <o0> Flash Base Address <0x0-0xFFFFFFFF:8> - <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> - </h> - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00080000; - -/*--------------------- DTCM RAM Configuration ---------------------------- - <h> RAM Configuration - <o0> RAM Base Address <0x0-0xFFFFFFFF:8> - <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - </h> - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00080000; - -/*--------------------- Embedded SRAM Configuration ---------------------------- - <h> SRAM Configuration - <o0> SRAM Base Address <0x0-0xFFFFFFFF:8> - <o1> SRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - </h> - -----------------------------------------------------------------------------*/ -__SRAM_BASE = 0x21000000; -__SRAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- - <h> Stack / Heap Configuration - <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - </h> - -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00008000; __HEAP_SIZE = 0x00008000; -/*--------------------- Embedded RAM Configuration ---------------------------- - <h> BRAM Configuration - <o0> BRAM Base Address <0x0-0xFFFFFFFF:8> - <o1> BRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> - </h> - -----------------------------------------------------------------------------*/ -__BRAM_BASE = 0x11000000; -__BRAM_SIZE = 0x00200000; - -/*--------------------- Embedded RAM Configuration ---------------------------- - <h> DDR Configuration - <o0> DDR Base Address <0x0-0xFFFFFFFF:8> - <o1> DDR Size (in Bytes) <0x0-0xFFFFFFFF:8> - </h> - -----------------------------------------------------------------------------*/ -__DDR_BASE = 0x60000000; -__DDR_SIZE = 0x02000000; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - MEMORY { - ITCM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - DTCM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE - SRAM (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE - BRAM (rwx) : ORIGIN = __BRAM_BASE, LENGTH = __BRAM_SIZE - DDR (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE + ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 + SRAM (rw) : ORIGIN = 0x11000000, LENGTH = 0x01000000 + DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 0x00080000 + DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x60000000 +} + +PHDRS +{ + rom_exec PT_LOAD; + rom_dram PT_LOAD; + null PT_NULL; } /* Linker script to place sections and symbol values. Should be used together @@ -117,6 +64,7 @@ MEMORY * __StackTop * __stack */ + ENTRY(Reset_Handler) SECTIONS @@ -146,7 +94,7 @@ SECTIONS *(.rodata*) KEEP(*(.eh_frame*)) - } > ITCM + } > ITCM :rom_exec /* * SG veneers: @@ -158,19 +106,19 @@ SECTIONS .gnu.sgstubs : { . = ALIGN(32); - } > ITCM + } > ITCM :rom_exec */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ITCM + } > ITCM :rom_exec - __exidx_start = .; .ARM.exidx : { + __exidx_start = .; *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ITCM __exidx_end = .; + } > ITCM :rom_exec .copy.table : { @@ -180,21 +128,20 @@ SECTIONS LONG (__data_start__) LONG (__data_end__ - __data_start__) - /* Add each additional data section here */ + LONG (__eddr_data) + LONG (__sram_data_start__) + LONG (__sram_data_end__ - __sram_data_start__ ) + __copy_table_end__ = .; - } > ITCM + } > ITCM :rom_exec .zero.table : { . = ALIGN(4); __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) -*/ + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) __zero_table_end__ = .; - } > ITCM /** * Location counter can end up 2byte aligned with narrow Thumb code but @@ -203,7 +150,9 @@ SECTIONS */ __etext = ALIGN (4); - .data : AT (__etext) + } > ITCM :rom_exec + + .data : AT(__etext) { __data_start__ = .; *(vtable) @@ -235,31 +184,9 @@ SECTIONS /* All data end */ __data_end__ = .; - } > DTCM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ + } > DTCM :rom_exec - .sram : + .sram.bss : { . = ALIGN(16); #ifdef ETHOSU_FAST_MEMORY_SIZE @@ -267,26 +194,28 @@ SECTIONS #else *(.bss.tensor_arena) #endif - - . = ALIGN(16); - *(.sram.data) - } > BRAM AT > BRAM + *.(output_data_sec) + } > SRAM :null .ddr : { - . = ALIGN(16); #ifdef ETHOSU_FAST_MEMORY_SIZE + . = ALIGN(16); *(.bss.tensor_arena) #endif - . = ALIGN(16); + . = ALIGN(4); *(input_data_sec) - . = ALIGN(16); *(network_model_sec) - - . = ALIGN (16); *(expected_output_data_sec) - } > DDR AT > DDR + } > DDR :rom_dram + + __eddr_data = ALIGN (16) ; + .sram.data : { + __sram_data_start__ = .; + *(.sram.data) + __sram_data_end__ = .; + } > SRAM AT >DDR :rom_dram .bss : { @@ -297,26 +226,7 @@ SECTIONS *(COMMON) . = ALIGN(4); __bss_end__ = .; - } > DTCM AT > DTCM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ + } > DTCM :null .heap (COPY) : { @@ -326,7 +236,7 @@ SECTIONS . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; - } > DTCM + } > DTCM :null .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : { @@ -335,7 +245,7 @@ SECTIONS . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; - } > DTCM + } > DTCM :null PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds DTCM limit */ |