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| author | Nir Ekhauz <nir.ekhauz@arm.com> | 2021-10-04 12:21:17 +0300 |
|---|---|---|
| committer | Nir Ekhauz <nir.ekhauz@arm.com> | 2021-10-18 12:21:37 +0300 |
| commit | a58edd81f99bb0516d7043f61488f579ef89a337 (patch) | |
| tree | 44db8406bea331fd46a92d334cb85dd524ae967e /targets | |
| parent | 52fddd00d0eb547d41074046c9f587a3a0679298 (diff) | |
| download | ethos-u-core-platform-a58edd81f99bb0516d7043f61488f579ef89a337.tar.gz | |
Configure timing adapter in run_platform.py
Change-Id: Ib108298417980a586bed8c8b4e0bb5e57f238316
Diffstat (limited to 'targets')
| -rw-r--r-- | targets/corstone-300/CMakeLists.txt | 11 | ||||
| -rw-r--r-- | targets/corstone-300/target.cpp | 114 |
2 files changed, 124 insertions, 1 deletions
diff --git a/targets/corstone-300/CMakeLists.txt b/targets/corstone-300/CMakeLists.txt index bd73481..12902d3 100644 --- a/targets/corstone-300/CMakeLists.txt +++ b/targets/corstone-300/CMakeLists.txt @@ -96,6 +96,17 @@ else() ETHOSU_ARENA=0) endif() +# AXI Timing adaptors +set(registers MAXR MAXW MAXRW RLATENCY WLATENCY PULSE_ON PULSE_OFF BWCAP PERFCTRL PERFCNT MODE HISTBIN HISTCNT) + +foreach(register ${registers}) + foreach(index RANGE 0 1) + set(name ETHOSU_TA_${register}_${index}) + set(${name} -1 CACHE STRING "${name}") + target_compile_definitions(ethosu_target_common INTERFACE ${name}=${${name}}) + endforeach() +endforeach() + # Linker script set(LINK_FILE platform CACHE STRING "Link file") diff --git a/targets/corstone-300/target.cpp b/targets/corstone-300/target.cpp index 541d4a5..b780c09 100644 --- a/targets/corstone-300/target.cpp +++ b/targets/corstone-300/target.cpp @@ -63,10 +63,119 @@ __attribute__((aligned(16), section(".bss.ethosu_scratch"))) uint8_t ethosu_scra struct ethosu_driver ethosu0_driver; #endif +/**************************************************************************** + * Timing Adapters + ****************************************************************************/ + +#if ETHOSU_TA_MAXR_0 < 0 +#define ETHOSU_TA_MAXR_0 0 +#endif +#if ETHOSU_TA_MAXW_0 < 0 +#define ETHOSU_TA_MAXW_0 0 +#endif +#if ETHOSU_TA_MAXRW_0 < 0 +#define ETHOSU_TA_MAXRW_0 0 +#endif +#if ETHOSU_TA_RLATENCY_0 < 0 +#define ETHOSU_TA_RLATENCY_0 0 +#endif +#if ETHOSU_TA_WLATENCY_0 < 0 +#define ETHOSU_TA_WLATENCY_0 0 +#endif +#if ETHOSU_TA_PULSE_ON_0 < 0 +#define ETHOSU_TA_PULSE_ON_0 0 +#endif +#if ETHOSU_TA_PULSE_OFF_0 < 0 +#define ETHOSU_TA_PULSE_OFF_0 0 +#endif +#if ETHOSU_TA_BWCAP_0 < 0 +#define ETHOSU_TA_BWCAP_0 0 +#endif +#if ETHOSU_TA_PERFCTRL_0 < 0 +#define ETHOSU_TA_PERFCTRL_0 0 +#endif +#if ETHOSU_TA_PERFCNT_0 < 0 +#define ETHOSU_TA_PERFCNT_0 0 +#endif +#if ETHOSU_TA_MODE_0 < 0 +#define ETHOSU_TA_MODE_0 0 +#endif +#if ETHOSU_TA_HISTBIN_0 < 0 +#define ETHOSU_TA_HISTBIN_0 0 +#endif +#if ETHOSU_TA_HISTCNT_0 < 0 +#define ETHOSU_TA_HISTCNT_0 0 +#endif + +#if ETHOSU_TA_MAXR_1 < 0 +#define ETHOSU_TA_MAXR_1 0 +#endif +#if ETHOSU_TA_MAXW_1 < 0 +#define ETHOSU_TA_MAXW_1 0 +#endif +#if ETHOSU_TA_MAXRW_1 < 0 +#define ETHOSU_TA_MAXRW_1 0 +#endif +#if ETHOSU_TA_RLATENCY_1 < 0 +#define ETHOSU_TA_RLATENCY_1 0 +#endif +#if ETHOSU_TA_WLATENCY_1 < 0 +#define ETHOSU_TA_WLATENCY_1 0 +#endif +#if ETHOSU_TA_PULSE_ON_1 < 0 +#define ETHOSU_TA_PULSE_ON_1 0 +#endif +#if ETHOSU_TA_PULSE_OFF_1 < 0 +#define ETHOSU_TA_PULSE_OFF_1 0 +#endif +#if ETHOSU_TA_BWCAP_1 < 0 +#define ETHOSU_TA_BWCAP_1 0 +#endif +#if ETHOSU_TA_PERFCTRL_1 < 0 +#define ETHOSU_TA_PERFCTRL_1 0 +#endif +#if ETHOSU_TA_PERFCNT_1 < 0 +#define ETHOSU_TA_PERFCNT_1 0 +#endif +#if ETHOSU_TA_MODE_1 < 0 +#define ETHOSU_TA_MODE_1 0 +#endif +#if ETHOSU_TA_HISTBIN_1 < 0 +#define ETHOSU_TA_HISTBIN_1 0 +#endif +#if ETHOSU_TA_HISTCNT_1 < 0 +#define ETHOSU_TA_HISTCNT_1 0 +#endif + static uintptr_t ethosu_ta_base_addrs[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT] = { {ETHOSU0_TA0_BASE_ADDRESS, ETHOSU0_TA1_BASE_ADDRESS}}; struct timing_adapter ethosu_ta[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT]; - +struct timing_adapter_settings ethosu_ta_settings[ETHOSU_NPU_TA_COUNT] = {{ETHOSU_TA_MAXR_0, + ETHOSU_TA_MAXW_0, + ETHOSU_TA_MAXRW_0, + ETHOSU_TA_RLATENCY_0, + ETHOSU_TA_WLATENCY_0, + ETHOSU_TA_PULSE_ON_0, + ETHOSU_TA_PULSE_OFF_0, + ETHOSU_TA_BWCAP_0, + ETHOSU_TA_PERFCTRL_0, + ETHOSU_TA_PERFCNT_0, + ETHOSU_TA_MODE_0, + ETHOSU_TA_HISTBIN_0, + ETHOSU_TA_HISTCNT_0}, + {ETHOSU_TA_MAXR_1, + ETHOSU_TA_MAXW_1, + ETHOSU_TA_MAXRW_1, + ETHOSU_TA_RLATENCY_1, + ETHOSU_TA_WLATENCY_1, + ETHOSU_TA_PULSE_ON_1, + ETHOSU_TA_PULSE_OFF_1, + ETHOSU_TA_BWCAP_1, + ETHOSU_TA_PERFCTRL_1, + ETHOSU_TA_PERFCNT_1, + ETHOSU_TA_MODE_1, + ETHOSU_TA_HISTBIN_1, + ETHOSU_TA_HISTCNT_1}}; /**************************************************************************** * Cache maintenance ****************************************************************************/ @@ -152,6 +261,9 @@ void targetSetup() { for (int j = 0; j < ETHOSU_NPU_TA_COUNT; j++) { if (ta_init(ðosu_ta[i][j], ethosu_ta_base_addrs[i][j])) { printf("Failed to initialize timing-adapter %d for NPU %d\n", j, i); + } else { + // Set the updated configuration + ta_set_all(ðosu_ta[i][j], ðosu_ta_settings[j]); } } } |