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| author | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2021-11-26 16:10:43 +0100 |
|---|---|---|
| committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2021-12-02 12:17:25 +0100 |
| commit | 29467e04fbc15f53001c0c95227db34160b776e7 (patch) | |
| tree | ddf60ed434b7190c750d77fb692472eb89ea7115 /targets | |
| parent | 7cec916ffd20a5a7999465d107a116806d6c6e96 (diff) | |
| download | ethos-u-core-platform-29467e04fbc15f53001c0c95227db34160b776e7.tar.gz | |
Fixing compiler warnings
Adjusting toolchain files which compiler warnings to enable.
Fixing compiler warnings reported by Arm Clang and Arm GCC.
Change-Id: I715e875904ffd7ecfe994d3093cdf066373981b1
Diffstat (limited to 'targets')
| -rw-r--r-- | targets/corstone-300/mpu.cpp | 2 | ||||
| -rw-r--r-- | targets/corstone-300/target.cpp | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/targets/corstone-300/mpu.cpp b/targets/corstone-300/mpu.cpp index 645723c..1d30ce0 100644 --- a/targets/corstone-300/mpu.cpp +++ b/targets/corstone-300/mpu.cpp @@ -39,7 +39,7 @@ void dump() { #ifdef ARM_MPU_ARMV8_H uint32_t mpuRegions = (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; - printf("MPU available with " PRIu32 " regions.\n", mpuRegions); + printf("MPU available with %" PRIu32 " regions.\n", mpuRegions); printf(" PRIVDEFENA : %lx\n", (MPU->CTRL & MPU_CTRL_PRIVDEFENA_Msk) >> MPU_CTRL_PRIVDEFENA_Pos); printf(" HFNMIENA : %lx\n", (MPU->CTRL & MPU_CTRL_HFNMIENA_Msk) >> MPU_CTRL_HFNMIENA_Pos); diff --git a/targets/corstone-300/target.cpp b/targets/corstone-300/target.cpp index f979f85..88f98be 100644 --- a/targets/corstone-300/target.cpp +++ b/targets/corstone-300/target.cpp @@ -185,6 +185,7 @@ struct timing_adapter_settings ethosu_ta_settings[ETHOSU_NPU_TA_COUNT] = {{ETHOS ETHOSU_TA_PERFCTRL_0, ETHOSU_TA_PERFCNT_0, ETHOSU_TA_MODE_0, + 0, // Read only register ETHOSU_TA_HISTBIN_0, ETHOSU_TA_HISTCNT_0}, {ETHOSU_TA_MAXR_1, @@ -198,8 +199,10 @@ struct timing_adapter_settings ethosu_ta_settings[ETHOSU_NPU_TA_COUNT] = {{ETHOS ETHOSU_TA_PERFCTRL_1, ETHOSU_TA_PERFCNT_1, ETHOSU_TA_MODE_1, + 0, // Read only register ETHOSU_TA_HISTBIN_1, ETHOSU_TA_HISTCNT_1}}; + /**************************************************************************** * Cache maintenance ****************************************************************************/ |