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author | Jonny Svärd <jonny.svaerd@arm.com> | 2021-04-27 11:32:31 +0200 |
---|---|---|
committer | Jonny Svärd <jonny.svaerd@arm.com> | 2021-04-27 11:39:47 +0200 |
commit | e3b6b96e011b962488ce777b34d5ca4442fc1243 (patch) | |
tree | db637aa62762e935d8b408b5350d3b8d878d26ee /targets | |
parent | 991af2bd8fb6c79dfb317837353857f34a727b17 (diff) | |
download | ethos-u-core-platform-e3b6b96e011b962488ce777b34d5ca4442fc1243.tar.gz |
Add missing NS address' to S MPU config table
Note that the MPU is split between S and NS. Code running in
NS (non-secure) state will not have access to S regions, however
it will have access to NS regions unless the MPU_NS is configured
(or other security mechanisms like SAU/IDAU limits access).
The MPU for NS is not enabled or configured in this example code.
Change-Id: I6b07bda25e4dbb23e8c2afdfa01d82ca5611f21a
Diffstat (limited to 'targets')
-rw-r--r-- | targets/corstone-300/target.cpp | 51 |
1 files changed, 46 insertions, 5 deletions
diff --git a/targets/corstone-300/target.cpp b/targets/corstone-300/target.cpp index a44c12f..5d93854 100644 --- a/targets/corstone-300/target.cpp +++ b/targets/corstone-300/target.cpp @@ -176,7 +176,7 @@ void targetSetup() { // MPU setup const std::vector<ARM_MPU_Region_t> mpuConfig = { { - // ITCM + // ITCM (NS) ARM_MPU_RBAR(0x00000000, // Base ARM_MPU_SH_NON, // Non-shareable 1, // Read-Only @@ -186,7 +186,7 @@ void targetSetup() { Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate }, { - // ITCM + // ITCM (S) ARM_MPU_RBAR(0x10000000, // Base ARM_MPU_SH_NON, // Non-shareable 1, // Read-Only @@ -196,7 +196,17 @@ void targetSetup() { Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate }, { - // FPGA DATA SRAM; BRAM + // FPGA DATA SRAM; BRAM (NS) + ARM_MPU_RBAR(0x01000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 0), // eXecute Never disabled + ARM_MPU_RLAR(0x011fffff, // Limit + Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + }, + { + // FPGA DATA SRAM; BRAM (S) ARM_MPU_RBAR(0x11000000, // Base ARM_MPU_SH_NON, // Non-shareable 0, // Read-Write @@ -206,7 +216,17 @@ void targetSetup() { Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate }, { - // DTCM + // DTCM (NS) + ARM_MPU_RBAR(0x20000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 1), // eXecute Never enabled + ARM_MPU_RLAR(0x2007ffff, // Limit + Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + }, + { + // DTCM (S) ARM_MPU_RBAR(0x30000000, // Base ARM_MPU_SH_NON, // Non-shareable 0, // Read-Write @@ -216,7 +236,17 @@ void targetSetup() { Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate }, { - // SSE-300 internal SRAM + // SSE-300 internal SRAM (NS) + ARM_MPU_RBAR(0x21000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 1), // eXecute Never enabled + ARM_MPU_RLAR(0x213fffff, // Limit + Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + }, + { + // SSE-300 internal SRAM (S) ARM_MPU_RBAR(0x31000000, // Base ARM_MPU_SH_NON, // Non-shareable 0, // Read-Write @@ -226,6 +256,17 @@ void targetSetup() { Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate }, { + // DDR (NS) + ARM_MPU_RBAR(0x60000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 1), // eXecute Never enabled + ARM_MPU_RLAR(0x6fffffff, // Limit + Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + }, + { + // DDR (S) ARM_MPU_RBAR(0x70000000, // Base ARM_MPU_SH_NON, // Non-shareable 0, // Read-Write |