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| author | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2021-10-19 10:54:47 +0200 |
|---|---|---|
| committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2021-10-19 12:40:19 +0000 |
| commit | 64f37cde5db1576056abe8940f73992ba3128bee (patch) | |
| tree | 39726930faf8b09d84a21cf88150449d010a0b68 /targets/corstone-300/target.cpp | |
| parent | 54350d6756f3bc824edefdd33563293828300f63 (diff) | |
| download | ethos-u-core-platform-64f37cde5db1576056abe8940f73992ba3128bee.tar.gz | |
Default timing adapters mode value
Setting default value for the timing adapters mode register.
Change-Id: I71efd96b8235d476a0d133c4f93cb97530172ab5
Diffstat (limited to 'targets/corstone-300/target.cpp')
| -rw-r--r-- | targets/corstone-300/target.cpp | 80 |
1 files changed, 52 insertions, 28 deletions
diff --git a/targets/corstone-300/target.cpp b/targets/corstone-300/target.cpp index b780c09..f979f85 100644 --- a/targets/corstone-300/target.cpp +++ b/targets/corstone-300/target.cpp @@ -67,83 +67,107 @@ struct ethosu_driver ethosu0_driver; * Timing Adapters ****************************************************************************/ -#if ETHOSU_TA_MAXR_0 < 0 +#ifndef ETHOSU_TA_MAXR_0 #define ETHOSU_TA_MAXR_0 0 #endif -#if ETHOSU_TA_MAXW_0 < 0 + +#ifndef ETHOSU_TA_MAXW_0 #define ETHOSU_TA_MAXW_0 0 #endif -#if ETHOSU_TA_MAXRW_0 < 0 + +#ifndef ETHOSU_TA_MAXRW_0 #define ETHOSU_TA_MAXRW_0 0 #endif -#if ETHOSU_TA_RLATENCY_0 < 0 + +#ifndef ETHOSU_TA_RLATENCY_0 #define ETHOSU_TA_RLATENCY_0 0 #endif -#if ETHOSU_TA_WLATENCY_0 < 0 + +#ifndef ETHOSU_TA_WLATENCY_0 #define ETHOSU_TA_WLATENCY_0 0 #endif -#if ETHOSU_TA_PULSE_ON_0 < 0 + +#ifndef ETHOSU_TA_PULSE_ON_0 #define ETHOSU_TA_PULSE_ON_0 0 #endif -#if ETHOSU_TA_PULSE_OFF_0 < 0 + +#ifndef ETHOSU_TA_PULSE_OFF_0 #define ETHOSU_TA_PULSE_OFF_0 0 #endif -#if ETHOSU_TA_BWCAP_0 < 0 + +#ifndef ETHOSU_TA_BWCAP_0 #define ETHOSU_TA_BWCAP_0 0 #endif -#if ETHOSU_TA_PERFCTRL_0 < 0 + +#ifndef ETHOSU_TA_PERFCTRL_0 #define ETHOSU_TA_PERFCTRL_0 0 #endif -#if ETHOSU_TA_PERFCNT_0 < 0 + +#ifndef ETHOSU_TA_PERFCNT_0 #define ETHOSU_TA_PERFCNT_0 0 #endif -#if ETHOSU_TA_MODE_0 < 0 -#define ETHOSU_TA_MODE_0 0 + +#ifndef ETHOSU_TA_MODE_0 +#define ETHOSU_TA_MODE_0 1 #endif -#if ETHOSU_TA_HISTBIN_0 < 0 + +#ifndef ETHOSU_TA_HISTBIN_0 #define ETHOSU_TA_HISTBIN_0 0 #endif -#if ETHOSU_TA_HISTCNT_0 < 0 + +#ifndef ETHOSU_TA_HISTCNT_0 #define ETHOSU_TA_HISTCNT_0 0 #endif -#if ETHOSU_TA_MAXR_1 < 0 +#ifndef ETHOSU_TA_MAXR_1 #define ETHOSU_TA_MAXR_1 0 #endif -#if ETHOSU_TA_MAXW_1 < 0 + +#ifndef ETHOSU_TA_MAXW_1 #define ETHOSU_TA_MAXW_1 0 #endif -#if ETHOSU_TA_MAXRW_1 < 0 + +#ifndef ETHOSU_TA_MAXRW_1 #define ETHOSU_TA_MAXRW_1 0 #endif -#if ETHOSU_TA_RLATENCY_1 < 0 + +#ifndef ETHOSU_TA_RLATENCY_1 #define ETHOSU_TA_RLATENCY_1 0 #endif -#if ETHOSU_TA_WLATENCY_1 < 0 + +#ifndef ETHOSU_TA_WLATENCY_1 #define ETHOSU_TA_WLATENCY_1 0 #endif -#if ETHOSU_TA_PULSE_ON_1 < 0 + +#ifndef ETHOSU_TA_PULSE_ON_1 #define ETHOSU_TA_PULSE_ON_1 0 #endif -#if ETHOSU_TA_PULSE_OFF_1 < 0 + +#ifndef ETHOSU_TA_PULSE_OFF_1 #define ETHOSU_TA_PULSE_OFF_1 0 #endif -#if ETHOSU_TA_BWCAP_1 < 0 + +#ifndef ETHOSU_TA_BWCAP_1 #define ETHOSU_TA_BWCAP_1 0 #endif -#if ETHOSU_TA_PERFCTRL_1 < 0 + +#ifndef ETHOSU_TA_PERFCTRL_1 #define ETHOSU_TA_PERFCTRL_1 0 #endif -#if ETHOSU_TA_PERFCNT_1 < 0 + +#ifndef ETHOSU_TA_PERFCNT_1 #define ETHOSU_TA_PERFCNT_1 0 #endif -#if ETHOSU_TA_MODE_1 < 0 -#define ETHOSU_TA_MODE_1 0 + +#ifndef ETHOSU_TA_MODE_1 +#define ETHOSU_TA_MODE_1 1 #endif -#if ETHOSU_TA_HISTBIN_1 < 0 + +#ifndef ETHOSU_TA_HISTBIN_1 #define ETHOSU_TA_HISTBIN_1 0 #endif -#if ETHOSU_TA_HISTCNT_1 < 0 + +#ifndef ETHOSU_TA_HISTCNT_1 #define ETHOSU_TA_HISTCNT_1 0 #endif |