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author | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2021-03-10 17:13:52 +0100 |
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committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2021-03-26 09:27:44 +0100 |
commit | b5f7cfe253dfeadd83caf60fde34b5b66f356782 (patch) | |
tree | f2286d8d1b7e1010c61277a80bdf344130c7322f /targets/corstone-300/platform.ld | |
parent | d66709083f08b4c32792d4a93e1e5b3c6b913fb2 (diff) | |
download | ethos-u-core-platform-b5f7cfe253dfeadd83caf60fde34b5b66f356782.tar.gz |
Driver unit tests
Add driver unit tests that runs simple command streams directly
on top of the NPU driver.
Change-Id: I3fcce2a2bfbd458d14186b8fd13ba47174f49562
Diffstat (limited to 'targets/corstone-300/platform.ld')
-rw-r--r-- | targets/corstone-300/platform.ld | 55 |
1 files changed, 29 insertions, 26 deletions
diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld index a1cdb0e..091a117 100644 --- a/targets/corstone-300/platform.ld +++ b/targets/corstone-300/platform.ld @@ -57,6 +57,15 @@ __STACK_SIZE = 0x00008000; __HEAP_SIZE = 0x00008000; /*--------------------- Embedded RAM Configuration ---------------------------- + <h> BRAM Configuration + <o0> BRAM Base Address <0x0-0xFFFFFFFF:8> + <o1> BRAM Size (in Bytes) <0x0-0xFFFFFFFF:8> + </h> + -----------------------------------------------------------------------------*/ +__BRAM_BASE = 0x11000000; +__BRAM_SIZE = 0x00200000; + +/*--------------------- Embedded RAM Configuration ---------------------------- <h> DDR Configuration <o0> DDR Base Address <0x0-0xFFFFFFFF:8> <o1> DDR Size (in Bytes) <0x0-0xFFFFFFFF:8> @@ -74,6 +83,7 @@ MEMORY ITCM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE DTCM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE SRAM (rwx) : ORIGIN = __SRAM_BASE, LENGTH = __SRAM_SIZE + BRAM (rwx) : ORIGIN = __BRAM_BASE, LENGTH = __BRAM_SIZE DDR (rwx) : ORIGIN = __DDR_BASE, LENGTH = __DDR_SIZE } @@ -141,7 +151,7 @@ SECTIONS /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option �--section-start� or in a linker script, + * must be set, either with the command line option '--section-start' or in a linker script, * to indicate where to place these veneers in memory. */ /* @@ -169,6 +179,7 @@ SECTIONS LONG (__etext) LONG (__data_start__) LONG (__data_end__ - __data_start__) + /* Add each additional data section here */ __copy_table_end__ = .; } > ITCM @@ -212,7 +223,6 @@ SECTIONS KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); @@ -249,28 +259,34 @@ SECTIONS } > RAM2 */ -#ifndef ETHOSU_FAST_MEMORY_SIZE - .sram : - { - . = ALIGN(16); - *(.bss.tensor_arena) - . = ALIGN(16); - } > SRAM AT > SRAM -#else .sram : { . = ALIGN(16); +#ifdef ETHOSU_FAST_MEMORY_SIZE *(.bss.ethosu_scratch); +#else + *(.bss.tensor_arena) +#endif + . = ALIGN(16); - } > SRAM AT > SRAM + *(.sram.data) + } > BRAM AT > BRAM - .bss.tensor_arena : + .ddr : { . = ALIGN(16); +#ifdef ETHOSU_FAST_MEMORY_SIZE *(.bss.tensor_arena) +#endif . = ALIGN(16); + *(input_data_sec) + + . = ALIGN(16); + *(network_model_sec) + + . = ALIGN (16); + *(expected_output_data_sec) } > DDR AT > DDR -#endif .bss : { @@ -283,7 +299,6 @@ SECTIONS __bss_end__ = .; } > DTCM AT > DTCM - /* * Secondary bss section, optional * @@ -303,18 +318,6 @@ SECTIONS } > RAM2 AT > RAM2 */ - .ddr : - { - /* __attribute__((aligned(16))) is not handled by the cmsis startup code. - * Force the alignement here as a workaround */ - . = ALIGN(4); - *(input_data_sec) - . = ALIGN(16); - *(network_model_sec) - *(expected_output_data_sec) - . = ALIGN (16); - } > DDR - .heap (COPY) : { . = ALIGN(8); |