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author | Anton Moberg <anton.moberg@arm.com> | 2021-04-08 09:50:57 +0200 |
---|---|---|
committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2021-04-21 11:52:19 +0000 |
commit | 908a07c61db978679a11a0f4ee023dc3c6aabffd (patch) | |
tree | f89e7ac6cea84695813783b579be144862886473 /applications/trustzone_inference/corstone-300/trustzone.h | |
parent | 2faaf409e57254fc0479695319b05f98a3de4821 (diff) | |
download | ethos-u-core-platform-908a07c61db978679a11a0f4ee023dc3c6aabffd.tar.gz |
Fix formatting
Fixed code formatting
Change-Id: I12df8da14a7100706f20ffb084ca8477928d0005
Diffstat (limited to 'applications/trustzone_inference/corstone-300/trustzone.h')
-rw-r--r-- | applications/trustzone_inference/corstone-300/trustzone.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/applications/trustzone_inference/corstone-300/trustzone.h b/applications/trustzone_inference/corstone-300/trustzone.h index 70fe717..9f145c3 100644 --- a/applications/trustzone_inference/corstone-300/trustzone.h +++ b/applications/trustzone_inference/corstone-300/trustzone.h @@ -90,14 +90,14 @@ #define BRAM_TOTAL_SIZE 0x00200000 #define BRAM_MPC 0x57000000 -#define SRAM0_BASE_S 0x31000000 -#define SRAM0_BASE_NS 0x21000000 -#define SRAM0_SIZE 0x00200000 -#define SRAM0_MPC 0x50083000 +#define SRAM0_BASE_S 0x31000000 +#define SRAM0_BASE_NS 0x21000000 +#define SRAM0_SIZE 0x00200000 +#define SRAM0_MPC 0x50083000 -#define DDR0_BASE_S 0x70000000 -#define DDR0_BASE_NS 0x60000000 -#define DDR0_SIZE 0x02000000 +#define DDR0_BASE_S 0x70000000 +#define DDR0_BASE_NS 0x60000000 +#define DDR0_SIZE 0x02000000 #ifdef TRUSTZONE_BUILD #define DDR_START DDR0_BASE_S @@ -105,7 +105,7 @@ #define DDR_START DDR0_BASE_NS #endif /* Separate DDRs for secure and nonsecure */ -#define DDR_SIZE DDR0_SIZE +#define DDR_SIZE DDR0_SIZE #if (S_TZ_ITCM_SIZE + TZ_NS_ITCM_SIZE) > ITCM_TOTAL_SIZE #error Missconfigured ITCM memory |