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| author | Ledion Daja <ledion.daja@arm.com> | 2022-02-02 15:26:53 +0100 |
|---|---|---|
| committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2022-02-02 15:03:44 +0000 |
| commit | 09d4945817ca235214a9b4f577b4b696f333ef00 (patch) | |
| tree | 0f5b50ea756df8e38e46c417d7882975e36a5141 | |
| parent | 47f556a5904578e1f87ffd4ea5103f68ce30426e (diff) | |
| download | ethos-u-core-platform-09d4945817ca235214a9b4f577b4b696f333ef00.tar.gz | |
Replace deprecated word to comply with inclusive language guidelines
Replace "master" word in the context of AXI protocol, with the
recommended word "manager".
Change-Id: If594db7ae96b3ad07afd156a8d788846f9bdb34d
| -rw-r--r-- | drivers/timing_adapter/include/timing_adapter.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/timing_adapter/include/timing_adapter.h b/drivers/timing_adapter/include/timing_adapter.h index ef4f9b9..45133cd 100644 --- a/drivers/timing_adapter/include/timing_adapter.h +++ b/drivers/timing_adapter/include/timing_adapter.h @@ -28,7 +28,7 @@ extern "C" { /** TIMING ADAPTER * * The timing adapter is an AXI-to-AXI bridge for providing well-defined memory timing - * to allow performance evaluation of an AXI master. The bridge works by delaying the + * to allow performance evaluation of an AXI manager. The bridge works by delaying the * responses from the memory according to run-time configurable parameters that can be * set in the timing adapter. Parameters include read and write response latencies, * no. of outstanding transactions, and a model of interferring traffic. |