From b64628f0aa412ae962e0398bf8c85271f19fb117 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonny=20Sv=C3=A4rd?= Date: Tue, 2 Jun 2020 15:24:54 +0200 Subject: Rework AXI patch to not depend on CMake Make ethosu_config.h define default macro's (with default values) unless the user overrides them. For CMake users, the macros can be defined on cmd line by specifying CMAKE_C_FLAGS for cmake, like: cmake ... -DCMAKE_C_FLAGS='-DFOO=1 -DBAR=2' Change-Id: I20fd3e07fdcfb7cba58da7198fd986f8821902bb --- CMakeLists.txt | 54 ++------------ src/ethosu_config.h | 194 +++++++++++++++++++++++++++++++++++++++++++++++++ src/ethosu_config.h.in | 44 ----------- 3 files changed, 199 insertions(+), 93 deletions(-) create mode 100644 src/ethosu_config.h delete mode 100644 src/ethosu_config.h.in diff --git a/CMakeLists.txt b/CMakeLists.txt index 91dc9d9..4651cf2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -54,6 +54,11 @@ if(DRIVER_LOG_SUPPORT) add_compile_definitions(LOG_ENABLED) endif() +# Enable PMU boot auto-initialization +if(DRIVER_PMU_AUTOINIT) + add_compile_definitions(PMU_AUTOINIT) +endif() + # Make include directories available for current- and sub projects include_directories(include src) include_directories(${CMSIS_PATH}/CMSIS/Core/Include) @@ -65,57 +70,8 @@ include_directories(${CMSIS_PATH}/CMSIS/Core/Include) # Build driver library add_library(ethosu_core_driver STATIC) target_include_directories(ethosu_core_driver PUBLIC include) -target_include_directories(ethosu_core_driver PRIVATE "${PROJECT_BINARY_DIR}/src") target_sources(ethosu_core_driver PRIVATE src/ethosu_driver.c src/ethosu_device.c src/ethosu_pmu.c) -# Configurables -set(NPU_QCONFIG "2" CACHE STRING "Default QCONFIG") -set(NPU_REGIONCFG_0 "3" CACHE STRING "Default region config 0") -set(NPU_REGIONCFG_1 "0" CACHE STRING "Default region config 1") -set(NPU_REGIONCFG_2 "1" CACHE STRING "Default region config 2") -set(NPU_REGIONCFG_3 "1" CACHE STRING "Default region config 3") -set(NPU_REGIONCFG_4 "1" CACHE STRING "Default region config 4") -set(NPU_REGIONCFG_5 "1" CACHE STRING "Default region config 5") -set(NPU_REGIONCFG_6 "1" CACHE STRING "Default region config 6") -set(NPU_REGIONCFG_7 "1" CACHE STRING "Default region config 7") - -set(AXI_LIMIT0_MAX_BEATS_BYTES "0x0" CACHE STRING "Default AXI_LIMIT0_MAX_BEATS_BYTES ") -set(AXI_LIMIT0_MEM_TYPE "0x0" CACHE STRING "Default AXI_LIMIT0_MEM_TYPE ") -set(AXI_LIMIT0_MAX_OUTSTANDING_READS "32" CACHE STRING "Default AXI_LIMIT0_MAX_OUTSTANDING_READS ") -set(AXI_LIMIT0_MAX_OUTSTANDING_WRITES "16" CACHE STRING "Default AXI_LIMIT0_MAX_OUTSTANDING_WRITES ") -set(AXI_LIMIT1_MAX_BEATS_BYTES "0x0" CACHE STRING "Default AXI_LIMIT1_MAX_BEATS_BYTES ") -set(AXI_LIMIT1_MEM_TYPE "0x0" CACHE STRING "Default AXI_LIMIT1_MEM_TYPE ") -set(AXI_LIMIT1_MAX_OUTSTANDING_READS "32" CACHE STRING "Default AXI_LIMIT1_MAX_OUTSTANDING_READS ") -set(AXI_LIMIT1_MAX_OUTSTANDING_WRITES "16" CACHE STRING "Default AXI_LIMIT1_MAX_OUTSTANDING_WRITES ") -set(AXI_LIMIT2_MAX_BEATS_BYTES "0x0" CACHE STRING "Default AXI_LIMIT2_MAX_BEATS_BYTES ") -set(AXI_LIMIT2_MEM_TYPE "0x0" CACHE STRING "Default AXI_LIMIT2_MEM_TYPE ") -set(AXI_LIMIT2_MAX_OUTSTANDING_READS "32" CACHE STRING "Default AXI_LIMIT2_MAX_OUTSTANDING_READS ") -set(AXI_LIMIT2_MAX_OUTSTANDING_WRITES "16" CACHE STRING "Default AXI_LIMIT2_MAX_OUTSTANDING_WRITES ") -set(AXI_LIMIT3_MAX_BEATS_BYTES "0x0" CACHE STRING "Default AXI_LIMIT3_MAX_BEATS_BYTES ") -set(AXI_LIMIT3_MEM_TYPE "0x0" CACHE STRING "Default AXI_LIMIT3_MEM_TYPE ") -set(AXI_LIMIT3_MAX_OUTSTANDING_READS "32" CACHE STRING "Default AXI_LIMIT3_MAX_OUTSTANDING_READS ") -set(AXI_LIMIT3_MAX_OUTSTANDING_WRITES "16" CACHE STRING "Default AXI_LIMIT3_MAX_OUTSTANDING_WRITES ") - - -# PMU -if(DRIVER_PMU_AUTOINIT) - set(PMU_AUTOINIT TRUE) - set(INIT_PMCR "0x0" CACHE STRING "Register control b0 = CNT_EN = Enable counters (RW), b1 = EVENT_CNT_RST = Reset event counters (WO), b2 = CYCLE_CNT_RST = Reset cycle counter (WO), b[15:11] = Number of event counters (RO)") - set(INIT_PMCNTENSET "0x0" CACHE STRING "Bit k enables event counter k. k=31 enables the cycle counter. Read value is current status.") - set(INIT_PMCNTENCLR "0x0" CACHE STRING "Bit k disables event counter k. k=31 disables the cycle counter. Reda value is current status.") - set(INIT_PMOVSSET "0x0" CACHE STRING "Overflow detection set. Bit k is for counter k. k=31 is cycle counter.") - set(INIT_PMOVSCLR "0x0" CACHE STRING "Overflow detection clear. Bit k is for counter k. k=31 is cycle counter.") - set(INIT_PMINTSET "0x0" CACHE STRING "Interrupt set. Bit k is for counter k. k=31 is cycle counter.") - set(INIT_PMINTCLR "0x8003" CACHE STRING "Interrupt clear. Bit k is for counter k. k=31 is cycle counter.") - set(INIT_PMCCNTR "0x0" CACHE STRING "Cycle counter, 48 bits value") - set(INIT_PMCCNTR_CFG "0x0" CACHE STRING "b[9:0] Start Event – this event number starts the cycle counter b[25:16] Stop Event – this event number stops the cycle counter") -endif() - -configure_file ( - "${PROJECT_SOURCE_DIR}/src/ethosu_config.h.in" - "${PROJECT_BINARY_DIR}/src/ethosu_config.h" -) - # # Print build status # diff --git a/src/ethosu_config.h b/src/ethosu_config.h new file mode 100644 index 0000000..07eb824 --- /dev/null +++ b/src/ethosu_config.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2019-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ETHOSU_CONFIG_H +#define ETHOSU_CONFIG_H + +/* Set default values if not manually overriden */ + +#ifndef NPU_QCONFIG +#define NPU_QCONFIG 2 +#endif + +#ifndef NPU_REGIONCFG_0 +#define NPU_REGIONCFG_0 3 +#endif + +#ifndef NPU_REGIONCFG_1 +#define NPU_REGIONCFG_1 0 +#endif + +#ifndef NPU_REGIONCFG_2 +#define NPU_REGIONCFG_2 1 +#endif + +#ifndef NPU_REGIONCFG_3 +#define NPU_REGIONCFG_3 1 +#endif + +#ifndef NPU_REGIONCFG_4 +#define NPU_REGIONCFG_4 1 +#endif + +#ifndef NPU_REGIONCFG_5 +#define NPU_REGIONCFG_5 1 +#endif + +#ifndef NPU_REGIONCFG_6 +#define NPU_REGIONCFG_6 1 +#endif + +#ifndef NPU_REGIONCFG_7 +#define NPU_REGIONCFG_7 1 +#endif + +#ifndef AXI_LIMIT0_MAX_BEATS_BYTES +#define AXI_LIMIT0_MAX_BEATS_BYTES 0x0 +#endif +#ifndef AXI_LIMIT0_MEM_TYPE +#define AXI_LIMIT0_MEM_TYPE 0x0 +#endif +#ifndef AXI_LIMIT0_MAX_OUTSTANDING_READS +#define AXI_LIMIT0_MAX_OUTSTANDING_READS 32 +#endif +#ifndef AXI_LIMIT0_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT0_MAX_OUTSTANDING_WRITES 16 +#endif + +#ifndef AXI_LIMIT1_MAX_BEATS_BYTES +#define AXI_LIMIT1_MAX_BEATS_BYTES 0x0 +#endif +#ifndef AXI_LIMIT1_MEM_TYPE +#define AXI_LIMIT1_MEM_TYPE 0x0 +#endif +#ifndef AXI_LIMIT1_MAX_OUTSTANDING_READS +#define AXI_LIMIT1_MAX_OUTSTANDING_READS 32 +#endif +#ifndef AXI_LIMIT1_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT1_MAX_OUTSTANDING_WRITES 16 +#endif + +#ifndef AXI_LIMIT2_MAX_BEATS_BYTES +#define AXI_LIMIT2_MAX_BEATS_BYTES 0x0 +#endif +#ifndef AXI_LIMIT2_MEM_TYPE +#define AXI_LIMIT2_MEM_TYPE 0x0 +#endif +#ifndef AXI_LIMIT2_MAX_OUTSTANDING_READS +#define AXI_LIMIT2_MAX_OUTSTANDING_READS 32 +#endif +#ifndef AXI_LIMIT2_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT2_MAX_OUTSTANDING_WRITES 16 +#endif +#ifndef AXI_LIMIT3_MAX_BEATS_BYTES +#define AXI_LIMIT3_MAX_BEATS_BYTES 0x0 +#endif +#ifndef AXI_LIMIT3_MEM_TYPE +#define AXI_LIMIT3_MEM_TYPE 0x0 +#endif +#ifndef AXI_LIMIT3_MAX_OUTSTANDING_READS +#define AXI_LIMIT3_MAX_OUTSTANDING_READS 32 +#endif +#ifndef AXI_LIMIT3_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT3_MAX_OUTSTANDING_WRITES 16 +#endif + +#ifdef PMU_AUTOINIT +/* + * Register control + * b0 = CNT_EN = Enable counters (RW) + * b1 = EVENT_CNT_RST = Reset event counters (WO) + * b2 = CYCLE_CNT_RST = Reset cycle counter (WO) + * b[15:11] = Number of event counters (RO) + */ +#ifndef INIT_PMCR +#define INIT_PMCR 0x0 +#endif + +/* + * Bit k enables event counter k + * k=31 enables the cycle counter + * Read value is current status + */ +#ifndef INIT_PMCNTENSET +#define INIT_PMCNTENSET 0x0 +#endif + +/* + * Bit k disables event counter k + * k=31 disables the cycle counter + * Read value is current status + */ +#ifndef INIT_PMCNTENCLR +#define INIT_PMCNTENCLR 0x0 +#endif + +/* + * Overflow detection set + * Bit k is for counter k + * k=31 is cycle counter + */ +#ifndef INIT_PMOVSSET +#define INIT_PMOVSSET 0x0 +#endif + +/* + * Overflow detection clear + * Bit k is for counter k + * k=31 is cycle counter + */ +#ifndef INIT_PMOVSCLR +#define INIT_PMOVSCLR 0x0 +#endif + +/* + * Interrupt set + * Bit k is for counter k + * k=31 is cycle counter + */ +#ifndef INIT_PMINTSET +#define INIT_PMINTSET 0x0 +#endif + +/* + * Interrupt clear + * Bit k is for counter k + * k=31 is cycle counter + */ +#ifndef INIT_PMINTCLR +#define INIT_PMINTCLR 0x8003 +#endif + +/* Cycle counter + * 48 bits value + */ +#ifndef INIT_PMCCNTR +#define INIT_PMCCNTR 0x0 +#endif + +/* + * b[9:0] Start Event – this event number starts the cycle counter + * b[25:16] Stop Event – this event number stops the cycle counter + */ +#ifndef INIT_PMCCNTR_CFG +#define INIT_PMCCNTR_CFG 0x0 +#endif + +#endif /* #ifdef PMU_AUTOINIT */ + +#endif /* #ifndef ETHOSU_CONFIG_H */ diff --git a/src/ethosu_config.h.in b/src/ethosu_config.h.in deleted file mode 100644 index 61cd591..0000000 --- a/src/ethosu_config.h.in +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef ethosu_config_h -#define ethosu_config_h -#include - -#define NPU_QCONFIG (@NPU_QCONFIG@) -#define NPU_REGIONCFG_0 (@NPU_REGIONCFG_0@) -#define NPU_REGIONCFG_1 (@NPU_REGIONCFG_1@) -#define NPU_REGIONCFG_2 (@NPU_REGIONCFG_2@) -#define NPU_REGIONCFG_3 (@NPU_REGIONCFG_3@) -#define NPU_REGIONCFG_4 (@NPU_REGIONCFG_4@) -#define NPU_REGIONCFG_5 (@NPU_REGIONCFG_5@) -#define NPU_REGIONCFG_6 (@NPU_REGIONCFG_6@) -#define NPU_REGIONCFG_7 (@NPU_REGIONCFG_7@) - -#define AXI_LIMIT0_MAX_BEATS_BYTES (@AXI_LIMIT0_MAX_BEATS_BYTES@) -#define AXI_LIMIT0_MEM_TYPE (@AXI_LIMIT0_MEM_TYPE@) -#define AXI_LIMIT0_MAX_OUTSTANDING_READS ((uint8_t)@AXI_LIMIT0_MAX_OUTSTANDING_READS@) -#define AXI_LIMIT0_MAX_OUTSTANDING_WRITES ((uint8_t)@AXI_LIMIT0_MAX_OUTSTANDING_WRITES@) -#define AXI_LIMIT1_MAX_BEATS_BYTES (@AXI_LIMIT1_MAX_BEATS_BYTES@) -#define AXI_LIMIT1_MEM_TYPE (@AXI_LIMIT1_MEM_TYPE@) -#define AXI_LIMIT1_MAX_OUTSTANDING_READS ((uint8_t)@AXI_LIMIT1_MAX_OUTSTANDING_READS@) -#define AXI_LIMIT1_MAX_OUTSTANDING_WRITES ((uint8_t)@AXI_LIMIT1_MAX_OUTSTANDING_WRITES@) -#define AXI_LIMIT2_MAX_BEATS_BYTES (@AXI_LIMIT2_MAX_BEATS_BYTES@) -#define AXI_LIMIT2_MEM_TYPE (@AXI_LIMIT2_MEM_TYPE@) -#define AXI_LIMIT2_MAX_OUTSTANDING_READS ((uint8_t)@AXI_LIMIT2_MAX_OUTSTANDING_READS@) -#define AXI_LIMIT2_MAX_OUTSTANDING_WRITES ((uint8_t)@AXI_LIMIT2_MAX_OUTSTANDING_WRITES@) -#define AXI_LIMIT3_MAX_BEATS_BYTES (@AXI_LIMIT3_MAX_BEATS_BYTES@) -#define AXI_LIMIT3_MEM_TYPE (@AXI_LIMIT3_MEM_TYPE@) -#define AXI_LIMIT3_MAX_OUTSTANDING_READS ((uint8_t)@AXI_LIMIT3_MAX_OUTSTANDING_READS@) -#define AXI_LIMIT3_MAX_OUTSTANDING_WRITES ((uint8_t)@AXI_LIMIT3_MAX_OUTSTANDING_WRITES@) - - -#cmakedefine PMU_AUTOINIT -#cmakedefine INIT_PMCR (@INIT_PMCR@) -#cmakedefine INIT_PMCNTENSET (@INIT_PMCNTENSET@) -#cmakedefine INIT_PMCNTENCLR (@INIT_PMCNTENCLR@) -#cmakedefine INIT_PMOVSSET (@INIT_PMOVSSET@) -#cmakedefine INIT_PMOVSCLR (@INIT_PMOVSCLR@) -#cmakedefine INIT_PMINTSET (@INIT_PMINTSET@) -#cmakedefine INIT_PMINTCLR (@INIT_PMINTCLR@) -#cmakedefine INIT_PMCCNTR (@INIT_PMCCNTR@) -#cmakedefine INIT_PMCCNTR_CFG (@INIT_PMCCNTR_CFG@) - -#endif -- cgit v1.2.1