diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/pmu_ethosu.h | 198 |
1 files changed, 194 insertions, 4 deletions
diff --git a/include/pmu_ethosu.h b/include/pmu_ethosu.h index b717130..a271114 100644 --- a/include/pmu_ethosu.h +++ b/include/pmu_ethosu.h @@ -1,6 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2019-2022 Arm Limited and/or its affiliates <open-source-office@arm.com> - * + * SPDX-FileCopyrightText: Copyright 2019-2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -22,7 +21,6 @@ /***************************************************************************** * Includes *****************************************************************************/ - #include <stdint.h> #include "ethosu_driver.h" @@ -34,13 +32,23 @@ extern "C" { /***************************************************************************** * Defines *****************************************************************************/ - +#ifdef ETHOSU85 +#define ETHOSU_PMU_NCOUNTERS 8 +#else #define ETHOSU_PMU_NCOUNTERS 4 +#endif #define ETHOSU_PMU_CNT1_Msk (1UL << 0) #define ETHOSU_PMU_CNT2_Msk (1UL << 1) #define ETHOSU_PMU_CNT3_Msk (1UL << 2) #define ETHOSU_PMU_CNT4_Msk (1UL << 3) +#ifdef ETHOSU85 +#define ETHOSU_PMU_CNT5_Msk (1UL << 4) +#define ETHOSU_PMU_CNT6_Msk (1UL << 5) +#define ETHOSU_PMU_CNT7_Msk (1UL << 6) +#define ETHOSU_PMU_CNT8_Msk (1UL << 7) +#endif + #define ETHOSU_PMU_CCNT_Msk (1UL << 31) /***************************************************************************** @@ -52,6 +60,7 @@ extern "C" { * Note: These values are symbolic. Actual HW-values may change. I.e. always use API * to set/get actual event-type value. * */ +#if defined(ETHOSU55) || defined(ETHOSU65) enum ethosu_pmu_event_type { ETHOSU_PMU_NO_EVENT = 0, @@ -131,6 +140,187 @@ enum ethosu_pmu_event_type ETHOSU_PMU_SENTINEL // End-marker (not event) }; +#elif defined(ETHOSU85) +enum ethosu_pmu_event_type +{ + ETHOSU_PMU_NO_EVENT = 0, + ETHOSU_PMU_CYCLE, + ETHOSU_PMU_NPU_IDLE, + ETHOSU_PMU_CC_STALLED_ON_BLOCKDEP, + ETHOSU_PMU_CC_STALLED_ON_SHRAM_RECONFIG, + ETHOSU_PMU_NPU_ACTIVE, + ETHOSU_PMU_MAC_ACTIVE, + ETHOSU_PMU_MAC_DPU_ACTIVE, + ETHOSU_PMU_MAC_STALLED_BY_W_OR_ACC, + ETHOSU_PMU_MAC_STALLED_BY_W, + ETHOSU_PMU_MAC_STALLED_BY_ACC, + ETHOSU_PMU_MAC_STALLED_BY_IB, + ETHOSU_PMU_AO_ACTIVE, + ETHOSU_PMU_AO_STALLED_BY_BS_OR_OB, + ETHOSU_PMU_AO_STALLED_BY_BS, + ETHOSU_PMU_AO_STALLED_BY_OB, + ETHOSU_PMU_AO_STALLED_BY_AB_OR_CB, + ETHOSU_PMU_AO_STALLED_BY_AB, + ETHOSU_PMU_AO_STALLED_BY_CB, + ETHOSU_PMU_WD_ACTIVE, + ETHOSU_PMU_WD_STALLED, + ETHOSU_PMU_WD_STALLED_BY_WD_BUF, + ETHOSU_PMU_WD_STALLED_BY_WS_FC, + ETHOSU_PMU_WD_STALLED_BY_WS_TC, + ETHOSU_PMU_WD_TRANS_WBLK, + ETHOSU_PMU_WD_TRANS_WS_FC, + ETHOSU_PMU_WD_TRANS_WS_TC, + ETHOSU_PMU_WD_STALLED_BY_WS_SC0, + ETHOSU_PMU_WD_STALLED_BY_WS_SC1, + ETHOSU_PMU_WD_STALLED_BY_WS_SC2, + ETHOSU_PMU_WD_STALLED_BY_WS_SC3, + ETHOSU_PMU_WD_PARSE_ACTIVE_SC0, + ETHOSU_PMU_WD_PARSE_ACTIVE_SC1, + ETHOSU_PMU_WD_PARSE_ACTIVE_SC2, + ETHOSU_PMU_WD_PARSE_ACTIVE_SC3, + ETHOSU_PMU_WD_PARSE_STALL_SC0, + ETHOSU_PMU_WD_PARSE_STALL_SC1, + ETHOSU_PMU_WD_PARSE_STALL_SC2, + ETHOSU_PMU_WD_PARSE_STALL_SC3, + ETHOSU_PMU_WD_PARSE_STALL_IN_SC0, + ETHOSU_PMU_WD_PARSE_STALL_IN_SC1, + ETHOSU_PMU_WD_PARSE_STALL_IN_SC2, + ETHOSU_PMU_WD_PARSE_STALL_IN_SC3, + ETHOSU_PMU_WD_PARSE_STALL_OUT_SC0, + ETHOSU_PMU_WD_PARSE_STALL_OUT_SC1, + ETHOSU_PMU_WD_PARSE_STALL_OUT_SC2, + ETHOSU_PMU_WD_PARSE_STALL_OUT_SC3, + ETHOSU_PMU_WD_TRANS_WS_SC0, + ETHOSU_PMU_WD_TRANS_WS_SC1, + ETHOSU_PMU_WD_TRANS_WS_SC2, + ETHOSU_PMU_WD_TRANS_WS_SC3, + ETHOSU_PMU_WD_TRANS_WB0, + ETHOSU_PMU_WD_TRANS_WB1, + ETHOSU_PMU_WD_TRANS_WB2, + ETHOSU_PMU_WD_TRANS_WB3, + ETHOSU_PMU_SRAM_RD_TRANS_ACCEPTED, + ETHOSU_PMU_SRAM_RD_TRANS_COMPLETED, + ETHOSU_PMU_SRAM_RD_DATA_BEAT_RECEIVED, + ETHOSU_PMU_SRAM_RD_TRAN_REQ_STALLED, + ETHOSU_PMU_SRAM_WR_TRANS_ACCEPTED, + ETHOSU_PMU_SRAM_WR_TRANS_COMPLETED_M, + ETHOSU_PMU_SRAM_WR_TRANS_COMPLETED_S, + ETHOSU_PMU_SRAM_WR_DATA_BEAT_WRITTEN, + ETHOSU_PMU_SRAM_WR_TRAN_REQ_STALLED, + ETHOSU_PMU_SRAM_WR_DATA_BEAT_STALLED, + ETHOSU_PMU_SRAM_ENABLED_CYCLES, + ETHOSU_PMU_SRAM_RD_STALL_LIMIT, + ETHOSU_PMU_SRAM_WR_STALL_LIMIT, + ETHOSU_PMU_AXI_LATENCY_ANY, + ETHOSU_PMU_AXI_LATENCY_32, + ETHOSU_PMU_AXI_LATENCY_64, + ETHOSU_PMU_AXI_LATENCY_128, + ETHOSU_PMU_AXI_LATENCY_256, + ETHOSU_PMU_AXI_LATENCY_512, + ETHOSU_PMU_AXI_LATENCY_1024, + ETHOSU_PMU_ECC_DMA, + ETHOSU_PMU_ECC_MAC_IB, + ETHOSU_PMU_ECC_MAC_AB, + ETHOSU_PMU_ECC_AO_CB, + ETHOSU_PMU_ECC_AO_OB, + ETHOSU_PMU_ECC_AO_LUT, + ETHOSU_PMU_EXT_RD_TRANS_ACCEPTED, + ETHOSU_PMU_EXT_RD_TRANS_COMPLETED, + ETHOSU_PMU_EXT_RD_DATA_BEAT_RECEIVED, + ETHOSU_PMU_EXT_RD_TRAN_REQ_STALLED, + ETHOSU_PMU_EXT_WR_TRANS_ACCEPTED, + ETHOSU_PMU_EXT_WR_TRANS_COMPLETED_M, + ETHOSU_PMU_EXT_WR_TRANS_COMPLETED_S, + ETHOSU_PMU_EXT_WR_DATA_BEAT_WRITTEN, + ETHOSU_PMU_EXT_WR_TRAN_REQ_STALLED, + ETHOSU_PMU_EXT_WR_DATA_BEAT_STALLED, + ETHOSU_PMU_EXT_ENABLED_CYCLES, + ETHOSU_PMU_EXT_RD_STALL_LIMIT, + ETHOSU_PMU_EXT_WR_STALL_LIMIT, + ETHOSU_PMU_SRAM0_RD_TRANS_ACCEPTED, + ETHOSU_PMU_SRAM0_RD_TRANS_COMPLETED, + ETHOSU_PMU_SRAM0_RD_DATA_BEAT_RECEIVED, + ETHOSU_PMU_SRAM0_RD_TRAN_REQ_STALLED, + ETHOSU_PMU_SRAM0_WR_TRANS_ACCEPTED, + ETHOSU_PMU_SRAM0_WR_TRANS_COMPLETED_M, + ETHOSU_PMU_SRAM0_WR_TRANS_COMPLETED_S, + ETHOSU_PMU_SRAM0_WR_DATA_BEAT_WRITTEN, + ETHOSU_PMU_SRAM0_WR_TRAN_REQ_STALLED, + ETHOSU_PMU_SRAM0_WR_DATA_BEAT_STALLED, + ETHOSU_PMU_SRAM0_ENABLED_CYCLES, + ETHOSU_PMU_SRAM0_RD_STALL_LIMIT, + ETHOSU_PMU_SRAM0_WR_STALL_LIMIT, + ETHOSU_PMU_SRAM1_RD_TRANS_ACCEPTED, + ETHOSU_PMU_SRAM1_RD_TRANS_COMPLETED, + ETHOSU_PMU_SRAM1_RD_DATA_BEAT_RECEIVED, + ETHOSU_PMU_SRAM1_RD_TRAN_REQ_STALLED, + ETHOSU_PMU_SRAM1_WR_TRANS_ACCEPTED, + ETHOSU_PMU_SRAM1_WR_TRANS_COMPLETED_M, + ETHOSU_PMU_SRAM1_WR_TRANS_COMPLETED_S, + ETHOSU_PMU_SRAM1_WR_DATA_BEAT_WRITTEN, + ETHOSU_PMU_SRAM1_WR_TRAN_REQ_STALLED, + ETHOSU_PMU_SRAM1_WR_DATA_BEAT_STALLED, + ETHOSU_PMU_SRAM1_ENABLED_CYCLES, + ETHOSU_PMU_SRAM1_RD_STALL_LIMIT, + ETHOSU_PMU_SRAM1_WR_STALL_LIMIT, + ETHOSU_PMU_SRAM2_RD_TRANS_ACCEPTED, + ETHOSU_PMU_SRAM2_RD_TRANS_COMPLETED, + ETHOSU_PMU_SRAM2_RD_DATA_BEAT_RECEIVED, + ETHOSU_PMU_SRAM2_RD_TRAN_REQ_STALLED, + ETHOSU_PMU_SRAM2_WR_TRANS_ACCEPTED, + ETHOSU_PMU_SRAM2_WR_TRANS_COMPLETED_M, + ETHOSU_PMU_SRAM2_WR_TRANS_COMPLETED_S, + ETHOSU_PMU_SRAM2_WR_DATA_BEAT_WRITTEN, + ETHOSU_PMU_SRAM2_WR_TRAN_REQ_STALLED, + ETHOSU_PMU_SRAM2_WR_DATA_BEAT_STALLED, + ETHOSU_PMU_SRAM2_ENABLED_CYCLES, + ETHOSU_PMU_SRAM2_RD_STALL_LIMIT, + ETHOSU_PMU_SRAM2_WR_STALL_LIMIT, + ETHOSU_PMU_SRAM3_RD_TRANS_ACCEPTED, + ETHOSU_PMU_SRAM3_RD_TRANS_COMPLETED, + ETHOSU_PMU_SRAM3_RD_DATA_BEAT_RECEIVED, + ETHOSU_PMU_SRAM3_RD_TRAN_REQ_STALLED, + ETHOSU_PMU_SRAM3_WR_TRANS_ACCEPTED, + ETHOSU_PMU_SRAM3_WR_TRANS_COMPLETED_M, + ETHOSU_PMU_SRAM3_WR_TRANS_COMPLETED_S, + ETHOSU_PMU_SRAM3_WR_DATA_BEAT_WRITTEN, + ETHOSU_PMU_SRAM3_WR_TRAN_REQ_STALLED, + ETHOSU_PMU_SRAM3_WR_DATA_BEAT_STALLED, + ETHOSU_PMU_SRAM3_ENABLED_CYCLES, + ETHOSU_PMU_SRAM3_RD_STALL_LIMIT, + ETHOSU_PMU_SRAM3_WR_STALL_LIMIT, + ETHOSU_PMU_EXT0_RD_TRANS_ACCEPTED, + ETHOSU_PMU_EXT0_RD_TRANS_COMPLETED, + ETHOSU_PMU_EXT0_RD_DATA_BEAT_RECEIVED, + ETHOSU_PMU_EXT0_RD_TRAN_REQ_STALLED, + ETHOSU_PMU_EXT0_WR_TRANS_ACCEPTED, + ETHOSU_PMU_EXT0_WR_TRANS_COMPLETED_M, + ETHOSU_PMU_EXT0_WR_TRANS_COMPLETED_S, + ETHOSU_PMU_EXT0_WR_DATA_BEAT_WRITTEN, + ETHOSU_PMU_EXT0_WR_TRAN_REQ_STALLED, + ETHOSU_PMU_EXT0_WR_DATA_BEAT_STALLED, + ETHOSU_PMU_EXT0_ENABLED_CYCLES, + ETHOSU_PMU_EXT0_RD_STALL_LIMIT, + ETHOSU_PMU_EXT0_WR_STALL_LIMIT, + ETHOSU_PMU_EXT1_RD_TRANS_ACCEPTED, + ETHOSU_PMU_EXT1_RD_TRANS_COMPLETED, + ETHOSU_PMU_EXT1_RD_DATA_BEAT_RECEIVED, + ETHOSU_PMU_EXT1_RD_TRAN_REQ_STALLED, + ETHOSU_PMU_EXT1_WR_TRANS_ACCEPTED, + ETHOSU_PMU_EXT1_WR_TRANS_COMPLETED_M, + ETHOSU_PMU_EXT1_WR_TRANS_COMPLETED_S, + ETHOSU_PMU_EXT1_WR_DATA_BEAT_WRITTEN, + ETHOSU_PMU_EXT1_WR_TRAN_REQ_STALLED, + ETHOSU_PMU_EXT1_WR_DATA_BEAT_STALLED, + ETHOSU_PMU_EXT1_ENABLED_CYCLES, + ETHOSU_PMU_EXT1_RD_STALL_LIMIT, + ETHOSU_PMU_EXT1_WR_STALL_LIMIT, + + ETHOSU_PMU_SENTINEL // End-marker (not event) +}; +#else +#error No NPU target defined +#endif /***************************************************************************** * Functions |