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| author | Douglas Troha <douglas.troha@arm.com> | 2020-05-14 20:28:31 +0200 |
|---|---|---|
| committer | Douglas Troha <douglas.troha@arm.com> | 2020-05-18 09:13:13 +0100 |
| commit | 2e7e3b70bf7d0c783b692b9062abca509f0a43b8 (patch) | |
| tree | 21b18b87087990c60432248a7cbf7c60ee2aca4b /src | |
| parent | daa0d20f69a7aa382eef78ca2e8110c11ee11893 (diff) | |
| download | ethos-u-core-driver-2e7e3b70bf7d0c783b692b9062abca509f0a43b8.tar.gz | |
Include 0.180 in HI 1.0
* Rename debug_addr to debug_address and update page names
Signed-off-by: Douglas Troha <douglas.troha@arm.com>
Change-Id: I1e4a820769dd00ec04e65e8027ae0d4b872c2d52
Diffstat (limited to 'src')
| -rw-r--r-- | src/ethosu55_interface.h | 4501 | ||||
| -rw-r--r-- | src/ethosu_device.c | 4 |
2 files changed, 2253 insertions, 2252 deletions
diff --git a/src/ethosu55_interface.h b/src/ethosu55_interface.h index fbe9279..a399c3b 100644 --- a/src/ethosu55_interface.h +++ b/src/ethosu55_interface.h @@ -45,7 +45,106 @@ // Register offsets // -// Register subpage DEBUG_INTERNAL +// Register subpage BASE +// +#define NPU_REG_ID 0x0000 +#define NPU_REG_STATUS 0x0004 +#define NPU_REG_CMD 0x0008 +#define NPU_REG_RESET 0x000C +#define NPU_REG_QBASE0 0x0010 +#define NPU_REG_QBASE1 0x0014 +#define NPU_REG_QREAD 0x0018 +#define NPU_REG_QCONFIG 0x001C +#define NPU_REG_QSIZE 0x0020 +#define NPU_REG_PROT 0x0024 +#define NPU_REG_CONFIG 0x0028 +#define NPU_REG_LOCK 0x002C +#define NPU_REG_REGIONCFG 0x003C +#define NPU_REG_AXI_LIMIT0 0x0040 +#define NPU_REG_AXI_LIMIT1 0x0044 +#define NPU_REG_AXI_LIMIT2 0x0048 +#define NPU_REG_AXI_LIMIT3 0x004C +#define BASE_REGISTERS_SIZE 0x0050 + +// +// Register subpage BASE_POINTERS +// +#define NPU_REG_BASEP0 0x0080 +#define NPU_REG_BASEP1 0x0084 +#define NPU_REG_BASEP2 0x0088 +#define NPU_REG_BASEP3 0x008C +#define NPU_REG_BASEP4 0x0090 +#define NPU_REG_BASEP5 0x0094 +#define NPU_REG_BASEP6 0x0098 +#define NPU_REG_BASEP7 0x009C +#define NPU_REG_BASEP8 0x00A0 +#define NPU_REG_BASEP9 0x00A4 +#define NPU_REG_BASEP10 0x00A8 +#define NPU_REG_BASEP11 0x00AC +#define NPU_REG_BASEP12 0x00B0 +#define NPU_REG_BASEP13 0x00B4 +#define NPU_REG_BASEP14 0x00B8 +#define NPU_REG_BASEP15 0x00BC +#define BASE_POINTERS_REGISTERS_SIZE 0x00C0 + +// +// Register subpage DEBUG +// +#define NPU_REG_WD_STATUS 0x0100 +#define NPU_REG_MAC_STATUS 0x0104 +#define NPU_REG_AO_STATUS 0x0108 +#define NPU_REG_DMA_STATUS0 0x0110 +#define NPU_REG_DMA_STATUS1 0x0114 +#define NPU_REG_CLKFORCE 0x0140 +#define NPU_REG_DEBUG_ADDRESS 0x0144 +#define NPU_REG_DEBUG_MISC 0x0148 +#define NPU_REG_DEBUGCORE 0x014C +#define DEBUG_REGISTERS_SIZE 0x0150 + +// +// Register subpage ID +// +#define NPU_REG_REVISION 0x0FC0 +#define NPU_REG_PID4 0x0FD0 +#define NPU_REG_PID5 0x0FD4 +#define NPU_REG_PID6 0x0FD8 +#define NPU_REG_PID7 0x0FDC +#define NPU_REG_PID0 0x0FE0 +#define NPU_REG_PID1 0x0FE4 +#define NPU_REG_PID2 0x0FE8 +#define NPU_REG_PID3 0x0FEC +#define NPU_REG_CID0 0x0FF0 +#define NPU_REG_CID1 0x0FF4 +#define NPU_REG_CID2 0x0FF8 +#define NPU_REG_CID3 0x0FFC +#define ID_REGISTERS_SIZE 0x1000 + +// +// Register subpage PMU +// +#define NPU_REG_PMCR 0x0180 +#define NPU_REG_PMCNTENSET 0x0184 +#define NPU_REG_PMCNTENCLR 0x0188 +#define NPU_REG_PMOVSSET 0x018C +#define NPU_REG_PMOVSCLR 0x0190 +#define NPU_REG_PMINTSET 0x0194 +#define NPU_REG_PMINTCLR 0x0198 +#define NPU_REG_PMCCNTR_LO 0x01A0 +#define NPU_REG_PMCCNTR_HI 0x01A4 +#define NPU_REG_PMCCNTR_CFG 0x01A8 +#define NPU_REG_PMCAXI_CHAN 0x01AC +#define NPU_REG_PMEVCNTR0 0x0300 +#define NPU_REG_PMEVCNTR1 0x0304 +#define NPU_REG_PMEVCNTR2 0x0308 +#define NPU_REG_PMEVCNTR3 0x030C +#define NPU_REG_PMEVTYPER0 0x0380 +#define NPU_REG_PMEVTYPER1 0x0384 +#define NPU_REG_PMEVTYPER2 0x0388 +#define NPU_REG_PMEVTYPER3 0x038C +#define PMU_REGISTERS_SIZE 0x0390 + +// +// Register subpage SHARED_BUFFER // #define NPU_REG_SHARED_BUFFER0 0x0400 #define NPU_REG_SHARED_BUFFER1 0x0404 @@ -303,109 +402,10 @@ #define NPU_REG_SHARED_BUFFER253 0x07F4 #define NPU_REG_SHARED_BUFFER254 0x07F8 #define NPU_REG_SHARED_BUFFER255 0x07FC -#define DEBUG_INTERNAL_REGISTERS_SIZE 0x0800 - -// -// Register subpage HW_DEBUG_INTERNAL -// -#define NPU_REG_WD_STATUS 0x0100 -#define NPU_REG_MAC_STATUS 0x0104 -#define NPU_REG_AO_STATUS 0x0108 -#define NPU_REG_DMA_STATUS0 0x0110 -#define NPU_REG_DMA_STATUS1 0x0114 -#define NPU_REG_CLKFORCE 0x0140 -#define NPU_REG_DEBUG_ADDR 0x0144 -#define NPU_REG_DEBUG_MISC 0x0148 -#define NPU_REG_DEBUGCORE 0x014C -#define HW_DEBUG_INTERNAL_REGISTERS_SIZE 0x0150 - -// -// Register subpage NPU_BP -// -#define NPU_REG_BASEP0 0x0080 -#define NPU_REG_BASEP1 0x0084 -#define NPU_REG_BASEP2 0x0088 -#define NPU_REG_BASEP3 0x008C -#define NPU_REG_BASEP4 0x0090 -#define NPU_REG_BASEP5 0x0094 -#define NPU_REG_BASEP6 0x0098 -#define NPU_REG_BASEP7 0x009C -#define NPU_REG_BASEP8 0x00A0 -#define NPU_REG_BASEP9 0x00A4 -#define NPU_REG_BASEP10 0x00A8 -#define NPU_REG_BASEP11 0x00AC -#define NPU_REG_BASEP12 0x00B0 -#define NPU_REG_BASEP13 0x00B4 -#define NPU_REG_BASEP14 0x00B8 -#define NPU_REG_BASEP15 0x00BC -#define NPU_BP_REGISTERS_SIZE 0x00C0 - -// -// Register subpage NPU_IDS -// -#define NPU_REG_REVISION 0x0FC0 -#define NPU_REG_PID4 0x0FD0 -#define NPU_REG_PID5 0x0FD4 -#define NPU_REG_PID6 0x0FD8 -#define NPU_REG_PID7 0x0FDC -#define NPU_REG_PID0 0x0FE0 -#define NPU_REG_PID1 0x0FE4 -#define NPU_REG_PID2 0x0FE8 -#define NPU_REG_PID3 0x0FEC -#define NPU_REG_CID0 0x0FF0 -#define NPU_REG_CID1 0x0FF4 -#define NPU_REG_CID2 0x0FF8 -#define NPU_REG_CID3 0x0FFC -#define NPU_IDS_REGISTERS_SIZE 0x1000 - -// -// Register subpage NPU_REG -// -#define NPU_REG_ID 0x0000 -#define NPU_REG_STATUS 0x0004 -#define NPU_REG_CMD 0x0008 -#define NPU_REG_RESET 0x000C -#define NPU_REG_QBASE0 0x0010 -#define NPU_REG_QBASE1 0x0014 -#define NPU_REG_QREAD 0x0018 -#define NPU_REG_QCONFIG 0x001C -#define NPU_REG_QSIZE 0x0020 -#define NPU_REG_PROT 0x0024 -#define NPU_REG_CONFIG 0x0028 -#define NPU_REG_LOCK 0x002C -#define NPU_REG_REGIONCFG 0x003C -#define NPU_REG_AXI_LIMIT0 0x0040 -#define NPU_REG_AXI_LIMIT1 0x0044 -#define NPU_REG_AXI_LIMIT2 0x0048 -#define NPU_REG_AXI_LIMIT3 0x004C -#define NPU_REG_REGISTERS_SIZE 0x0050 - -// -// Register subpage PMU -// -#define NPU_REG_PMCR 0x0180 -#define NPU_REG_PMCNTENSET 0x0184 -#define NPU_REG_PMCNTENCLR 0x0188 -#define NPU_REG_PMOVSSET 0x018C -#define NPU_REG_PMOVSCLR 0x0190 -#define NPU_REG_PMINTSET 0x0194 -#define NPU_REG_PMINTCLR 0x0198 -#define NPU_REG_PMCCNTR_LO 0x01A0 -#define NPU_REG_PMCCNTR_HI 0x01A4 -#define NPU_REG_PMCCNTR_CFG 0x01A8 -#define NPU_REG_PMCAXI_CHAN 0x01AC -#define NPU_REG_PMEVCNTR0 0x0300 -#define NPU_REG_PMEVCNTR1 0x0304 -#define NPU_REG_PMEVCNTR2 0x0308 -#define NPU_REG_PMEVCNTR3 0x030C -#define NPU_REG_PMEVTYPER0 0x0380 -#define NPU_REG_PMEVTYPER1 0x0384 -#define NPU_REG_PMEVTYPER2 0x0388 -#define NPU_REG_PMEVTYPER3 0x038C -#define PMU_REGISTERS_SIZE 0x0390 +#define SHARED_BUFFER_REGISTERS_SIZE 0x0800 // -// Register subpage TSU_DEBUG_INTERNAL +// Register subpage TSU // #define NPU_REG_IFM_PAD_TOP 0x0800 #define NPU_REG_IFM_PAD_LEFT 0x0804 @@ -526,10 +526,10 @@ #define NPU_REG_SCALE1_BASE 0x0B50 #define NPU_REG_SCALE1_BASE_HI 0x0B54 #define NPU_REG_SCALE1_LENGTH 0x0B58 -#define TSU_DEBUG_INTERNAL_REGISTERS_SIZE 0x0B5C +#define TSU_REGISTERS_SIZE 0x0B5C // -// Register subpage TSU_DEBUG_RO_INTERNAL +// Register subpage TSU_DEBUG // #define NPU_REG_KERNEL_X 0x0200 #define NPU_REG_KERNEL_Y 0x0204 @@ -566,7 +566,7 @@ #define NPU_REG_DMA_SCALE_SRC 0x0280 #define NPU_REG_DMA_SCALE_SRC_HI 0x0284 #define NPU_REG_CURRENT_CMD 0x02BC -#define TSU_DEBUG_RO_INTERNAL_REGISTERS_SIZE 0x02C0 +#define TSU_DEBUG_REGISTERS_SIZE 0x02C0 #ifdef __cplusplus @@ -1210,8 +1210,8 @@ enum stride_mode #endif -// wd_status_r - WD_STATUS of core DEBUGCORE -struct wd_status_r +// id_r - ID register +struct id_r { #ifdef __cplusplus private: @@ -1220,33 +1220,28 @@ struct wd_status_r { struct { - uint32_t core_slice_state : 2; // STATE_HEADER=0, STATE_PALETTE=1, STATE_WEIGHTS=2 - uint32_t core_idle : 1; // Core idle - uint32_t ctrl_state : 2; // IDLE=0, DRAIN=1, OFD_INIT=2, OFD_RUN=3 - uint32_t ctrl_idle : 1; // All stripe jobs idle (all weights consumed) - uint32_t write_buf_index0 : 3; // current write index for next data from core - uint32_t write_buf_valid0 : 1; // write buf valid (full) - uint32_t write_buf_idle0 : 1; // write buf idle (empty) - uint32_t write_buf_index1 : 3; // current write index for next data from core - uint32_t write_buf_valid1 : 1; // write buf valid (full) - uint32_t write_buf_idle1 : 1; // write buf idle (empty) - uint32_t events : 12; // WD events mapped as appendix A - uint32_t reserved0 : 4; + uint32_t version_status : 4; // This is the version of the product + uint32_t version_minor : 4; // This is the n for the P part of an RnPn release number + uint32_t version_major : 4; // This is the n for the R part of an RnPn release number + uint32_t product_major : 4; // This is the X part of the ML00X product number + uint32_t arch_patch_rev : 4; // This is the patch number of the architecture version a.b + uint32_t + arch_minor_rev : 8; // This is the minor architecture version number, b in the architecture version a.b + uint32_t + arch_major_rev : 4; // This is the major architecture version number, a in the architecture version a.b }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR wd_status_r() : - core_slice_state(static_cast<uint32_t>(0)), core_idle(static_cast<uint32_t>(0)), - ctrl_state(static_cast<uint32_t>(0)), ctrl_idle(static_cast<uint32_t>(0)), - write_buf_index0(static_cast<uint32_t>(0)), write_buf_valid0(static_cast<uint32_t>(0)), - write_buf_idle0(static_cast<uint32_t>(0)), write_buf_index1(static_cast<uint32_t>(0)), - write_buf_valid1(static_cast<uint32_t>(0)), write_buf_idle1(static_cast<uint32_t>(0)), - events(static_cast<uint32_t>(0)), reserved0(static_cast<uint32_t>(0)) + CONSTEXPR id_r() : + version_status(static_cast<uint32_t>(1)), version_minor(static_cast<uint32_t>(0x0)), + version_major(static_cast<uint32_t>(0x0)), product_major(static_cast<uint32_t>(4)), + arch_patch_rev(static_cast<uint32_t>(0)), arch_minor_rev(static_cast<uint32_t>(0)), + arch_major_rev(static_cast<uint32_t>(1)) { } - CONSTEXPR wd_status_r(uint32_t init) : word(init) {} + CONSTEXPR id_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -1263,180 +1258,120 @@ struct wd_status_r { return word; } - wd_status_r copy() volatile - { - return *this; - } - CONSTEXPR uint32_t get_core_slice_state() const - { - uint32_t value = static_cast<uint32_t>(core_slice_state); - return value; - } - uint32_t get_core_slice_state() const volatile - { - uint32_t value = static_cast<uint32_t>(core_slice_state); - return value; - } - CONSTEXPR wd_status_r &set_core_slice_state(uint32_t value) - { - core_slice_state = ((1u << 2) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_core_idle() const - { - uint32_t value = static_cast<uint32_t>(core_idle); - return value; - } - uint32_t get_core_idle() const volatile - { - uint32_t value = static_cast<uint32_t>(core_idle); - return value; - } - CONSTEXPR wd_status_r &set_core_idle(uint32_t value) - { - core_idle = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_ctrl_state() const - { - uint32_t value = static_cast<uint32_t>(ctrl_state); - return value; - } - uint32_t get_ctrl_state() const volatile - { - uint32_t value = static_cast<uint32_t>(ctrl_state); - return value; - } - CONSTEXPR wd_status_r &set_ctrl_state(uint32_t value) - { - ctrl_state = ((1u << 2) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_ctrl_idle() const - { - uint32_t value = static_cast<uint32_t>(ctrl_idle); - return value; - } - uint32_t get_ctrl_idle() const volatile - { - uint32_t value = static_cast<uint32_t>(ctrl_idle); - return value; - } - CONSTEXPR wd_status_r &set_ctrl_idle(uint32_t value) + id_r copy() volatile { - ctrl_idle = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_write_buf_index0() const + CONSTEXPR uint32_t get_version_status() const { - uint32_t value = static_cast<uint32_t>(write_buf_index0); + uint32_t value = static_cast<uint32_t>(version_status); return value; } - uint32_t get_write_buf_index0() const volatile + uint32_t get_version_status() const volatile { - uint32_t value = static_cast<uint32_t>(write_buf_index0); + uint32_t value = static_cast<uint32_t>(version_status); return value; } - CONSTEXPR wd_status_r &set_write_buf_index0(uint32_t value) + CONSTEXPR id_r &set_version_status(uint32_t value) { - write_buf_index0 = ((1u << 3) - 1) & static_cast<uint32_t>(value); + version_status = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_write_buf_valid0() const + CONSTEXPR uint32_t get_version_minor() const { - uint32_t value = static_cast<uint32_t>(write_buf_valid0); + uint32_t value = static_cast<uint32_t>(version_minor); return value; } - uint32_t get_write_buf_valid0() const volatile + uint32_t get_version_minor() const volatile { - uint32_t value = static_cast<uint32_t>(write_buf_valid0); + uint32_t value = static_cast<uint32_t>(version_minor); return value; } - CONSTEXPR wd_status_r &set_write_buf_valid0(uint32_t value) + CONSTEXPR id_r &set_version_minor(uint32_t value) { - write_buf_valid0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + version_minor = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_write_buf_idle0() const + CONSTEXPR uint32_t get_version_major() const { - uint32_t value = static_cast<uint32_t>(write_buf_idle0); + uint32_t value = static_cast<uint32_t>(version_major); return value; } - uint32_t get_write_buf_idle0() const volatile + uint32_t get_version_major() const volatile { - uint32_t value = static_cast<uint32_t>(write_buf_idle0); + uint32_t value = static_cast<uint32_t>(version_major); return value; } - CONSTEXPR wd_status_r &set_write_buf_idle0(uint32_t value) + CONSTEXPR id_r &set_version_major(uint32_t value) { - write_buf_idle0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + version_major = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_write_buf_index1() const + CONSTEXPR uint32_t get_product_major() const { - uint32_t value = static_cast<uint32_t>(write_buf_index1); + uint32_t value = static_cast<uint32_t>(product_major); return value; } - uint32_t get_write_buf_index1() const volatile + uint32_t get_product_major() const volatile { - uint32_t value = static_cast<uint32_t>(write_buf_index1); + uint32_t value = static_cast<uint32_t>(product_major); return value; } - CONSTEXPR wd_status_r &set_write_buf_index1(uint32_t value) + CONSTEXPR id_r &set_product_major(uint32_t value) { - write_buf_index1 = ((1u << 3) - 1) & static_cast<uint32_t>(value); + product_major = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_write_buf_valid1() const + CONSTEXPR uint32_t get_arch_patch_rev() const { - uint32_t value = static_cast<uint32_t>(write_buf_valid1); + uint32_t value = static_cast<uint32_t>(arch_patch_rev); return value; } - uint32_t get_write_buf_valid1() const volatile + uint32_t get_arch_patch_rev() const volatile { - uint32_t value = static_cast<uint32_t>(write_buf_valid1); + uint32_t value = static_cast<uint32_t>(arch_patch_rev); return value; } - CONSTEXPR wd_status_r &set_write_buf_valid1(uint32_t value) + CONSTEXPR id_r &set_arch_patch_rev(uint32_t value) { - write_buf_valid1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + arch_patch_rev = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_write_buf_idle1() const + CONSTEXPR uint32_t get_arch_minor_rev() const { - uint32_t value = static_cast<uint32_t>(write_buf_idle1); + uint32_t value = static_cast<uint32_t>(arch_minor_rev); return value; } - uint32_t get_write_buf_idle1() const volatile + uint32_t get_arch_minor_rev() const volatile { - uint32_t value = static_cast<uint32_t>(write_buf_idle1); + uint32_t value = static_cast<uint32_t>(arch_minor_rev); return value; } - CONSTEXPR wd_status_r &set_write_buf_idle1(uint32_t value) + CONSTEXPR id_r &set_arch_minor_rev(uint32_t value) { - write_buf_idle1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + arch_minor_rev = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_events() const + CONSTEXPR uint32_t get_arch_major_rev() const { - uint32_t value = static_cast<uint32_t>(events); + uint32_t value = static_cast<uint32_t>(arch_major_rev); return value; } - uint32_t get_events() const volatile + uint32_t get_arch_major_rev() const volatile { - uint32_t value = static_cast<uint32_t>(events); + uint32_t value = static_cast<uint32_t>(arch_major_rev); return value; } - CONSTEXPR wd_status_r &set_events(uint32_t value) + CONSTEXPR id_r &set_arch_major_rev(uint32_t value) { - events = ((1u << 12) - 1) & static_cast<uint32_t>(value); + arch_major_rev = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// mac_status_r - MAC_STATUS of core DEBUGCORE -struct mac_status_r +// status_r - Register describes the current operating status of the NPU +struct status_r { #ifdef __cplusplus private: @@ -1445,42 +1380,42 @@ struct mac_status_r { struct { - uint32_t block_cfg_valid : 1; // MAC has a valid block configuration - uint32_t trav_en : 1; // MAC is doing block traversal - uint32_t wait_for_ib : 1; // MAC is waiting for an Input Buffer to become available - uint32_t wait_for_acc_buf : 1; // MAC is waiting for an Accumulator Buffer to become available - uint32_t wait_for_weights : 1; // MAC is waiting for a Weight Block to become available - uint32_t stall_stripe : 1; // MAC is stalling between two stripes - uint32_t dw_sel : 1; // Currently used weight interface in MAC AI - uint32_t wait_for_dw0_ready : 1; // MAC AI is waiting for MAC DPU to send dw0_ready to WD - uint32_t wait_for_dw1_ready : 1; // MAC AI is waiting for MAC DPU to send dw1_ready to WD - uint32_t acc_buf_sel_ai : 1; // Currently used AccBuf interface in MAC AI - uint32_t wait_for_acc0_ready : 1; // MAC AI is waiting for acc0_ready from AO - uint32_t wait_for_acc1_ready : 1; // MAC AI is waiting for acc1_ready from AO - uint32_t acc_buf_sel_aa : 1; // Currently used AccBuf interface in MAC ADDER_ARRAY - uint32_t acc0_valid : 1; // MAC outgoing value of acc0_valid - uint32_t acc1_valid : 1; // MAC outgoing value of acc1_valid - uint32_t reserved0 : 1; - uint32_t events : 11; // Mapped to MAC events described in Appendix A - uint32_t reserved1 : 5; + uint32_t state : 1; // NPU state, 0 = Stopped, 1 = Running + uint32_t irq_raised : 1; // Raw IRQ status, 0 = IRQ not raised, 1 = IRQ raised. IRQ is cleared using command + // register bit 1 + uint32_t + bus_status : 1; // 0=OK, 1=Bus abort detected and processing halted (NPU will reach IDLE state and not + // to start process any more commands/AXI transactions). Can only be cleared by a reset + uint32_t reset_status : 1; // Reset is ongoing and only this register can be read (other registers read as 0 + // and writes are ignored.) A value of 0 means NPU is not being reset and can be + // accessed as normal + uint32_t + cmd_parse_error : 1; // 0=No error 1=Command stream parsing error detected. Can only be cleared by reset + uint32_t cmd_end_reached : 1; // 0=Not reached, 1=Reached. Cleared by writing QBASE or QSIZE when NPU is in + // stopped state + uint32_t pmu_irq_raised : 1; // 0=No PMU IRQ, 1=PMU IRQ raised. Cleared by using command register bit 1 + uint32_t wd_fault : 1; // Weight decoder state: 0=no fault 1=weight decoder decompression fault. Can only be + // cleared by reset + uint32_t reserved0 : 3; + uint32_t faulting_interface : 1; // Faulting interface on bus abort. 0=AXI-M0 1=AXI-M1 + uint32_t faulting_channel : 4; // Faulting channel on a bus abort. Read: 0=Cmd 1=IFM 2=Weights 3=Scale+Bias + // 4=Mem2Mem; Write: 8=OFM 9=Mem2Mem + uint32_t irq_history_mask : 16; // IRQ History mask }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR mac_status_r() : - block_cfg_valid(static_cast<uint32_t>(0)), trav_en(static_cast<uint32_t>(0)), - wait_for_ib(static_cast<uint32_t>(0)), wait_for_acc_buf(static_cast<uint32_t>(0)), - wait_for_weights(static_cast<uint32_t>(0)), stall_stripe(static_cast<uint32_t>(0)), - dw_sel(static_cast<uint32_t>(0)), wait_for_dw0_ready(static_cast<uint32_t>(0)), - wait_for_dw1_ready(static_cast<uint32_t>(0)), acc_buf_sel_ai(static_cast<uint32_t>(0)), - wait_for_acc0_ready(static_cast<uint32_t>(0)), wait_for_acc1_ready(static_cast<uint32_t>(0)), - acc_buf_sel_aa(static_cast<uint32_t>(0)), acc0_valid(static_cast<uint32_t>(0)), - acc1_valid(static_cast<uint32_t>(0)), reserved0(static_cast<uint32_t>(0)), events(static_cast<uint32_t>(0)), - reserved1(static_cast<uint32_t>(0)) + CONSTEXPR status_r() : + state(static_cast<uint32_t>(::state::STOPPED)), irq_raised(static_cast<uint32_t>(0x0)), + bus_status(static_cast<uint32_t>(0x0)), reset_status(static_cast<uint32_t>(0x1)), + cmd_parse_error(static_cast<uint32_t>(0x0)), cmd_end_reached(static_cast<uint32_t>(0x0)), + pmu_irq_raised(static_cast<uint32_t>(0x0)), wd_fault(static_cast<uint32_t>(0x0)), + reserved0(static_cast<uint32_t>(0)), faulting_interface(static_cast<uint32_t>(0x0)), + faulting_channel(static_cast<uint32_t>(0x0)), irq_history_mask(static_cast<uint32_t>(0x0)) { } - CONSTEXPR mac_status_r(uint32_t init) : word(init) {} + CONSTEXPR status_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -1497,255 +1432,180 @@ struct mac_status_r { return word; } - mac_status_r copy() volatile - { - return *this; - } - CONSTEXPR uint32_t get_block_cfg_valid() const - { - uint32_t value = static_cast<uint32_t>(block_cfg_valid); - return value; - } - uint32_t get_block_cfg_valid() const volatile - { - uint32_t value = static_cast<uint32_t>(block_cfg_valid); - return value; - } - CONSTEXPR mac_status_r &set_block_cfg_valid(uint32_t value) - { - block_cfg_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_trav_en() const - { - uint32_t value = static_cast<uint32_t>(trav_en); - return value; - } - uint32_t get_trav_en() const volatile - { - uint32_t value = static_cast<uint32_t>(trav_en); - return value; - } - CONSTEXPR mac_status_r &set_trav_en(uint32_t value) - { - trav_en = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_wait_for_ib() const - { - uint32_t value = static_cast<uint32_t>(wait_for_ib); - return value; - } - uint32_t get_wait_for_ib() const volatile - { - uint32_t value = static_cast<uint32_t>(wait_for_ib); - return value; - } - CONSTEXPR mac_status_r &set_wait_for_ib(uint32_t value) - { - wait_for_ib = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_wait_for_acc_buf() const - { - uint32_t value = static_cast<uint32_t>(wait_for_acc_buf); - return value; - } - uint32_t get_wait_for_acc_buf() const volatile - { - uint32_t value = static_cast<uint32_t>(wait_for_acc_buf); - return value; - } - CONSTEXPR mac_status_r &set_wait_for_acc_buf(uint32_t value) - { - wait_for_acc_buf = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_wait_for_weights() const - { - uint32_t value = static_cast<uint32_t>(wait_for_weights); - return value; - } - uint32_t get_wait_for_weights() const volatile - { - uint32_t value = static_cast<uint32_t>(wait_for_weights); - return value; - } - CONSTEXPR mac_status_r &set_wait_for_weights(uint32_t value) + status_r copy() volatile { - wait_for_weights = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_stall_stripe() const + CONSTEXPR ::state get_state() const { - uint32_t value = static_cast<uint32_t>(stall_stripe); + ::state value = static_cast<::state>(state); return value; } - uint32_t get_stall_stripe() const volatile + ::state get_state() const volatile { - uint32_t value = static_cast<uint32_t>(stall_stripe); + ::state value = static_cast<::state>(state); return value; } - CONSTEXPR mac_status_r &set_stall_stripe(uint32_t value) + CONSTEXPR status_r &set_state(::state value) { - stall_stripe = ((1u << 1) - 1) & static_cast<uint32_t>(value); + state = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_dw_sel() const + CONSTEXPR uint32_t get_irq_raised() const { - uint32_t value = static_cast<uint32_t>(dw_sel); + uint32_t value = static_cast<uint32_t>(irq_raised); return value; } - uint32_t get_dw_sel() const volatile + uint32_t get_irq_raised() const volatile { - uint32_t value = static_cast<uint32_t>(dw_sel); + uint32_t value = static_cast<uint32_t>(irq_raised); return value; } - CONSTEXPR mac_status_r &set_dw_sel(uint32_t value) + CONSTEXPR status_r &set_irq_raised(uint32_t value) { - dw_sel = ((1u << 1) - 1) & static_cast<uint32_t>(value); + irq_raised = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_wait_for_dw0_ready() const + CONSTEXPR uint32_t get_bus_status() const { - uint32_t value = static_cast<uint32_t>(wait_for_dw0_ready); + uint32_t value = static_cast<uint32_t>(bus_status); return value; } - uint32_t get_wait_for_dw0_ready() const volatile + uint32_t get_bus_status() const volatile { - uint32_t value = static_cast<uint32_t>(wait_for_dw0_ready); + uint32_t value = static_cast<uint32_t>(bus_status); return value; } - CONSTEXPR mac_status_r &set_wait_for_dw0_ready(uint32_t value) + CONSTEXPR status_r &set_bus_status(uint32_t value) { - wait_for_dw0_ready = ((1u << 1) - 1) & static_cast<uint32_t>(value); + bus_status = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_wait_for_dw1_ready() const + CONSTEXPR uint32_t get_reset_status() const { - uint32_t value = static_cast<uint32_t>(wait_for_dw1_ready); + uint32_t value = static_cast<uint32_t>(reset_status); return value; } - uint32_t get_wait_for_dw1_ready() const volatile + uint32_t get_reset_status() const volatile { - uint32_t value = static_cast<uint32_t>(wait_for_dw1_ready); + uint32_t value = static_cast<uint32_t>(reset_status); return value; } - CONSTEXPR mac_status_r &set_wait_for_dw1_ready(uint32_t value) + CONSTEXPR status_r &set_reset_status(uint32_t value) { - wait_for_dw1_ready = ((1u << 1) - 1) & static_cast<uint32_t>(value); + reset_status = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_acc_buf_sel_ai() const + CONSTEXPR uint32_t get_cmd_parse_error() const { - uint32_t value = static_cast<uint32_t>(acc_buf_sel_ai); + uint32_t value = static_cast<uint32_t>(cmd_parse_error); return value; } - uint32_t get_acc_buf_sel_ai() const volatile + uint32_t get_cmd_parse_error() const volatile { - uint32_t value = static_cast<uint32_t>(acc_buf_sel_ai); + uint32_t value = static_cast<uint32_t>(cmd_parse_error); return value; } - CONSTEXPR mac_status_r &set_acc_buf_sel_ai(uint32_t value) + CONSTEXPR status_r &set_cmd_parse_error(uint32_t value) { - acc_buf_sel_ai = ((1u << 1) - 1) & static_cast<uint32_t>(value); + cmd_parse_error = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_wait_for_acc0_ready() const + CONSTEXPR uint32_t get_cmd_end_reached() const { - uint32_t value = static_cast<uint32_t>(wait_for_acc0_ready); + uint32_t value = static_cast<uint32_t>(cmd_end_reached); return value; } - uint32_t get_wait_for_acc0_ready() const volatile + uint32_t get_cmd_end_reached() const volatile { - uint32_t value = static_cast<uint32_t>(wait_for_acc0_ready); + uint32_t value = static_cast<uint32_t>(cmd_end_reached); return value; } - CONSTEXPR mac_status_r &set_wait_for_acc0_ready(uint32_t value) + CONSTEXPR status_r &set_cmd_end_reached(uint32_t value) { - wait_for_acc0_ready = ((1u << 1) - 1) & static_cast<uint32_t>(value); + cmd_end_reached = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_wait_for_acc1_ready() const + CONSTEXPR uint32_t get_pmu_irq_raised() const { - uint32_t value = static_cast<uint32_t>(wait_for_acc1_ready); + uint32_t value = static_cast<uint32_t>(pmu_irq_raised); return value; } - uint32_t get_wait_for_acc1_ready() const volatile + uint32_t get_pmu_irq_raised() const volatile { - uint32_t value = static_cast<uint32_t>(wait_for_acc1_ready); + uint32_t value = static_cast<uint32_t>(pmu_irq_raised); return value; } - CONSTEXPR mac_status_r &set_wait_for_acc1_ready(uint32_t value) + CONSTEXPR status_r &set_pmu_irq_raised(uint32_t value) { - wait_for_acc1_ready = ((1u << 1) - 1) & static_cast<uint32_t>(value); + pmu_irq_raised = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_acc_buf_sel_aa() const + CONSTEXPR uint32_t get_wd_fault() const { - uint32_t value = static_cast<uint32_t>(acc_buf_sel_aa); + uint32_t value = static_cast<uint32_t>(wd_fault); return value; } - uint32_t get_acc_buf_sel_aa() const volatile + uint32_t get_wd_fault() const volatile { - uint32_t value = static_cast<uint32_t>(acc_buf_sel_aa); + uint32_t value = static_cast<uint32_t>(wd_fault); return value; } - CONSTEXPR mac_status_r &set_acc_buf_sel_aa(uint32_t value) + CONSTEXPR status_r &set_wd_fault(uint32_t value) { - acc_buf_sel_aa = ((1u << 1) - 1) & static_cast<uint32_t>(value); + wd_fault = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_acc0_valid() const + CONSTEXPR uint32_t get_faulting_interface() const { - uint32_t value = static_cast<uint32_t>(acc0_valid); + uint32_t value = static_cast<uint32_t>(faulting_interface); return value; } - uint32_t get_acc0_valid() const volatile + uint32_t get_faulting_interface() const volatile { - uint32_t value = static_cast<uint32_t>(acc0_valid); + uint32_t value = static_cast<uint32_t>(faulting_interface); return value; } - CONSTEXPR mac_status_r &set_acc0_valid(uint32_t value) + CONSTEXPR status_r &set_faulting_interface(uint32_t value) { - acc0_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + faulting_interface = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_acc1_valid() const + CONSTEXPR uint32_t get_faulting_channel() const { - uint32_t value = static_cast<uint32_t>(acc1_valid); + uint32_t value = static_cast<uint32_t>(faulting_channel); return value; } - uint32_t get_acc1_valid() const volatile + uint32_t get_faulting_channel() const volatile { - uint32_t value = static_cast<uint32_t>(acc1_valid); + uint32_t value = static_cast<uint32_t>(faulting_channel); return value; } - CONSTEXPR mac_status_r &set_acc1_valid(uint32_t value) + CONSTEXPR status_r &set_faulting_channel(uint32_t value) { - acc1_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + faulting_channel = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_events() const + CONSTEXPR uint32_t get_irq_history_mask() const { - uint32_t value = static_cast<uint32_t>(events); + uint32_t value = static_cast<uint32_t>(irq_history_mask); return value; } - uint32_t get_events() const volatile + uint32_t get_irq_history_mask() const volatile { - uint32_t value = static_cast<uint32_t>(events); + uint32_t value = static_cast<uint32_t>(irq_history_mask); return value; } - CONSTEXPR mac_status_r &set_events(uint32_t value) + CONSTEXPR status_r &set_irq_history_mask(uint32_t value) { - events = ((1u << 11) - 1) & static_cast<uint32_t>(value); + irq_history_mask = ((1u << 16) - 1) & static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// ao_status_r - AO_STATUS of core DEBUGCORE -struct ao_status_r +// cmd_r - Command register, reads as last written command +struct cmd_r { #ifdef __cplusplus private: @@ -1754,31 +1614,29 @@ struct ao_status_r { struct { - uint32_t cmd_sbw_valid : 1; // Block command to shared buffer write module is valid. - uint32_t cmd_act_valid : 1; // Block command to activation function module is valid. - uint32_t cmd_ctl_valid : 1; // Block command to control module is valid. - uint32_t cmd_scl_valid : 1; // Block command to scale module is valid. - uint32_t cmd_sbr_valid : 1; // Block command to shared buffer read module is valid. - uint32_t cmd_ofm_valid : 1; // Block command to ofm parameter module is valid. - uint32_t blk_cmd_ready : 1; // Ready to accept block command. - uint32_t blk_cmd_valid : 1; // Block command from CC is valid. - uint32_t reserved0 : 8; - uint32_t events : 8; // Mapped to AO events described in Appendix A. - uint32_t reserved1 : 8; + uint32_t transition_to_running_state : 1; // Write 1 to transition the NPU to running state. Writing 0 has + // no effect + uint32_t clear_irq : 1; // Write 1 to clear the IRQ status in the STATUS register. Writing 0 has no effect + uint32_t clock_q_enable : 1; // Write 1 to this bit to enable clock off using clock q-interface and enable + // the master clock gate + uint32_t power_q_enable : 1; // Write 1 to this bit to enable power off using power q-interface + uint32_t + stop_request : 1; // Write 1 to this bit to request STOP after completing any already-started commands + uint32_t reserved0 : 11; + uint32_t clear_irq_history : 16; // Clears the IRQ history mask }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR ao_status_r() : - cmd_sbw_valid(static_cast<uint32_t>(0)), cmd_act_valid(static_cast<uint32_t>(0)), - cmd_ctl_valid(static_cast<uint32_t>(0)), cmd_scl_valid(static_cast<uint32_t>(0)), - cmd_sbr_valid(static_cast<uint32_t>(0)), cmd_ofm_valid(static_cast<uint32_t>(0)), - blk_cmd_ready(static_cast<uint32_t>(0)), blk_cmd_valid(static_cast<uint32_t>(0)), - reserved0(static_cast<uint32_t>(0)), events(static_cast<uint32_t>(0)), reserved1(static_cast<uint32_t>(0)) + CONSTEXPR cmd_r() : + transition_to_running_state(static_cast<uint32_t>(0x0)), clear_irq(static_cast<uint32_t>(0x0)), + clock_q_enable(static_cast<uint32_t>(0x0)), power_q_enable(static_cast<uint32_t>(0x0)), + stop_request(static_cast<uint32_t>(0x0)), reserved0(static_cast<uint32_t>(0)), + clear_irq_history(static_cast<uint32_t>(0x0)) { } - CONSTEXPR ao_status_r(uint32_t init) : word(init) {} + CONSTEXPR cmd_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -1795,150 +1653,105 @@ struct ao_status_r { return word; } - ao_status_r copy() volatile - { - return *this; - } - CONSTEXPR uint32_t get_cmd_sbw_valid() const - { - uint32_t value = static_cast<uint32_t>(cmd_sbw_valid); - return value; - } - uint32_t get_cmd_sbw_valid() const volatile - { - uint32_t value = static_cast<uint32_t>(cmd_sbw_valid); - return value; - } - CONSTEXPR ao_status_r &set_cmd_sbw_valid(uint32_t value) - { - cmd_sbw_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_cmd_act_valid() const - { - uint32_t value = static_cast<uint32_t>(cmd_act_valid); - return value; - } - uint32_t get_cmd_act_valid() const volatile - { - uint32_t value = static_cast<uint32_t>(cmd_act_valid); - return value; - } - CONSTEXPR ao_status_r &set_cmd_act_valid(uint32_t value) - { - cmd_act_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_cmd_ctl_valid() const - { - uint32_t value = static_cast<uint32_t>(cmd_ctl_valid); - return value; - } - uint32_t get_cmd_ctl_valid() const volatile - { - uint32_t value = static_cast<uint32_t>(cmd_ctl_valid); - return value; - } - CONSTEXPR ao_status_r &set_cmd_ctl_valid(uint32_t value) + cmd_r copy() volatile { - cmd_ctl_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_cmd_scl_valid() const + CONSTEXPR uint32_t get_transition_to_running_state() const { - uint32_t value = static_cast<uint32_t>(cmd_scl_valid); + uint32_t value = static_cast<uint32_t>(transition_to_running_state); return value; } - uint32_t get_cmd_scl_valid() const volatile + uint32_t get_transition_to_running_state() const volatile { - uint32_t value = static_cast<uint32_t>(cmd_scl_valid); + uint32_t value = static_cast<uint32_t>(transition_to_running_state); return value; } - CONSTEXPR ao_status_r &set_cmd_scl_valid(uint32_t value) + CONSTEXPR cmd_r &set_transition_to_running_state(uint32_t value) { - cmd_scl_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + transition_to_running_state = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_cmd_sbr_valid() const + CONSTEXPR uint32_t get_clear_irq() const { - uint32_t value = static_cast<uint32_t>(cmd_sbr_valid); + uint32_t value = static_cast<uint32_t>(clear_irq); return value; } - uint32_t get_cmd_sbr_valid() const volatile + uint32_t get_clear_irq() const volatile { - uint32_t value = static_cast<uint32_t>(cmd_sbr_valid); + uint32_t value = static_cast<uint32_t>(clear_irq); return value; } - CONSTEXPR ao_status_r &set_cmd_sbr_valid(uint32_t value) + CONSTEXPR cmd_r &set_clear_irq(uint32_t value) { - cmd_sbr_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + clear_irq = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_cmd_ofm_valid() const + CONSTEXPR uint32_t get_clock_q_enable() const { - uint32_t value = static_cast<uint32_t>(cmd_ofm_valid); + uint32_t value = static_cast<uint32_t>(clock_q_enable); return value; } - uint32_t get_cmd_ofm_valid() const volatile + uint32_t get_clock_q_enable() const volatile { - uint32_t value = static_cast<uint32_t>(cmd_ofm_valid); + uint32_t value = static_cast<uint32_t>(clock_q_enable); return value; } - CONSTEXPR ao_status_r &set_cmd_ofm_valid(uint32_t value) + CONSTEXPR cmd_r &set_clock_q_enable(uint32_t value) { - cmd_ofm_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + clock_q_enable = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_blk_cmd_ready() const + CONSTEXPR uint32_t get_power_q_enable() const { - uint32_t value = static_cast<uint32_t>(blk_cmd_ready); + uint32_t value = static_cast<uint32_t>(power_q_enable); return value; } - uint32_t get_blk_cmd_ready() const volatile + uint32_t get_power_q_enable() const volatile { - uint32_t value = static_cast<uint32_t>(blk_cmd_ready); + uint32_t value = static_cast<uint32_t>(power_q_enable); return value; } - CONSTEXPR ao_status_r &set_blk_cmd_ready(uint32_t value) + CONSTEXPR cmd_r &set_power_q_enable(uint32_t value) { - blk_cmd_ready = ((1u << 1) - 1) & static_cast<uint32_t>(value); + power_q_enable = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_blk_cmd_valid() const + CONSTEXPR uint32_t get_stop_request() const { - uint32_t value = static_cast<uint32_t>(blk_cmd_valid); + uint32_t value = static_cast<uint32_t>(stop_request); return value; } - uint32_t get_blk_cmd_valid() const volatile + uint32_t get_stop_request() const volatile { - uint32_t value = static_cast<uint32_t>(blk_cmd_valid); + uint32_t value = static_cast<uint32_t>(stop_request); return value; } - CONSTEXPR ao_status_r &set_blk_cmd_valid(uint32_t value) + CONSTEXPR cmd_r &set_stop_request(uint32_t value) { - blk_cmd_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + stop_request = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_events() const + CONSTEXPR uint32_t get_clear_irq_history() const { - uint32_t value = static_cast<uint32_t>(events); + uint32_t value = static_cast<uint32_t>(clear_irq_history); return value; } - uint32_t get_events() const volatile + uint32_t get_clear_irq_history() const volatile { - uint32_t value = static_cast<uint32_t>(events); + uint32_t value = static_cast<uint32_t>(clear_irq_history); return value; } - CONSTEXPR ao_status_r &set_events(uint32_t value) + CONSTEXPR cmd_r &set_clear_irq_history(uint32_t value) { - events = ((1u << 8) - 1) & static_cast<uint32_t>(value); + clear_irq_history = ((1u << 16) - 1) & static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// dma_status0_r - DMA_STATUS0 of core DEBUGCORE -struct dma_status0_r +// reset_r - Request Reset and new security mode +struct reset_r { #ifdef __cplusplus private: @@ -1947,65 +1760,20 @@ struct dma_status0_r { struct { - uint32_t CMD_IDLE : 1; // When this bit is high means that the CMD block is not busy in generating addresses - // for a CMD job. - uint32_t IFM_IDLE : 1; // When this bit is high means that there are no ongoing IFM jobs - uint32_t WGT_IDLE_C0 : 1; // When this bit is high means that the WGT block is not busy in generating - // addresses for a WGT job - uint32_t BAS_IDLE_C0 : 1; // When this bit is high means that the BAS block is not busy in generating - // addresses for a BAS job - uint32_t M2M_IDLE : 1; // When this bit is high means that there are no ongoing M2M jobs - uint32_t OFM_IDLE : 1; // When this bit is high means that there are no ongoing OFM jobs - uint32_t HALT_REQ : 1; // CPM has requested to HALT AXI bus before soft reset - uint32_t HALT_ACK : 1; // DMA is in condition to halt the AXI bus since there are no pending transactions - uint32_t PAUSE_REQ : 1; // CC has requested to pause the AXI - uint32_t PAUSE_ACK : 1; // DMA is in condition to pause the AXI bus since there are no pending transactions - uint32_t IB0_AI_VALID_C0 : 1; // Data for AI to be read in IFM input buffer 0 - Core 0 - uint32_t IB0_AI_READY_C0 : 1; // Data consumed from AI in IFM input buffer 0 - Core 0 - uint32_t IB1_AI_VALID_C0 : 1; // Data for AI to be read in IFM input buffer 1 - Core 0 - uint32_t IB1_AI_READY_C0 : 1; // Data consumed from AI in IFM input buffer 1 - Core 0 - uint32_t IB0_AO_VALID_C0 : 1; // Data for AO to be read in IFM input buffer 0 - Core 0 - uint32_t IB0_AO_READY_C0 : 1; // Data consumed from AO in IFM input buffer 0 - Core 0 - uint32_t IB1_AO_VALID_C0 : 1; // Data for AO to be read in IFM input buffer 0 - Core 0 - uint32_t IB1_AO_READY_C0 : 1; // Data consumed from AO in IFM input buffer 1 - Core 0 - uint32_t OB0_VALID_C0 : 1; // Data for DMA ready to be consumed in OFM output buffer 0 - Core 0 - uint32_t OB0_READY_C0 : 1; // Data consumed from DMA in OFM output buffer 0 - Core 0 - uint32_t OB1_VALID_C0 : 1; // Data for DMA ready to be consumed in OFM output buffer 1 - Core 0 - uint32_t OB1_READY_C0 : 1; // Data consumed from DMA in OFM output buffer 1 - Core 0 - uint32_t CMD_VALID : 1; // New command word for CC to be consumed - uint32_t CMD_READY : 1; // command word consumed by CC - uint32_t WD_BITSTREAM_VALID_C0 : 1; // New weight word for WD to be consumed - Core 0 - uint32_t WD_BITSTREAM_READY_C0 : 1; // Weight word consumed by WD - Core 0 - uint32_t BS_BITSTREAM_VALID_C0 : 1; // New BaS word for AO to be consumed - Core 0 - uint32_t BS_BITSTREAM_READY_C0 : 1; // BaS word consumed by AO - Core 0 - uint32_t AXI0_AR_STALLED : 1; // Read transfer request stalled on arready low AXI0 (due to memory system) - uint32_t AXI0_RD_LIMIT_STALL : 1; // Read stalled due to one AXI0 limit counter being reached - uint32_t AXI0_AW_STALLED : 1; // Write transfer request stalled on awready low AXI0 (due to memory system) - uint32_t AXI0_W_STALLED : 1; // Write transfer stalled on awready low AXI0 (due to memory system) + uint32_t pending_CPL : 1; // Current privilege level 0=User 1=Privileged + uint32_t pending_CSL : 1; // Current security level 0=Secure 1=Non secure + uint32_t reserved0 : 30; }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR dma_status0_r() : - CMD_IDLE(static_cast<uint32_t>(0)), IFM_IDLE(static_cast<uint32_t>(0)), WGT_IDLE_C0(static_cast<uint32_t>(0)), - BAS_IDLE_C0(static_cast<uint32_t>(0)), M2M_IDLE(static_cast<uint32_t>(0)), OFM_IDLE(static_cast<uint32_t>(0)), - HALT_REQ(static_cast<uint32_t>(0)), HALT_ACK(static_cast<uint32_t>(0)), PAUSE_REQ(static_cast<uint32_t>(0)), - PAUSE_ACK(static_cast<uint32_t>(0)), IB0_AI_VALID_C0(static_cast<uint32_t>(0)), - IB0_AI_READY_C0(static_cast<uint32_t>(0)), IB1_AI_VALID_C0(static_cast<uint32_t>(0)), - IB1_AI_READY_C0(static_cast<uint32_t>(0)), IB0_AO_VALID_C0(static_cast<uint32_t>(0)), - IB0_AO_READY_C0(static_cast<uint32_t>(0)), IB1_AO_VALID_C0(static_cast<uint32_t>(0)), - IB1_AO_READY_C0(static_cast<uint32_t>(0)), OB0_VALID_C0(static_cast<uint32_t>(0)), - OB0_READY_C0(static_cast<uint32_t>(0)), OB1_VALID_C0(static_cast<uint32_t>(0)), - OB1_READY_C0(static_cast<uint32_t>(0)), CMD_VALID(static_cast<uint32_t>(0)), - CMD_READY(static_cast<uint32_t>(0)), WD_BITSTREAM_VALID_C0(static_cast<uint32_t>(0)), - WD_BITSTREAM_READY_C0(static_cast<uint32_t>(0)), BS_BITSTREAM_VALID_C0(static_cast<uint32_t>(0)), - BS_BITSTREAM_READY_C0(static_cast<uint32_t>(0)), AXI0_AR_STALLED(static_cast<uint32_t>(0)), - AXI0_RD_LIMIT_STALL(static_cast<uint32_t>(0)), AXI0_AW_STALLED(static_cast<uint32_t>(0)), - AXI0_W_STALLED(static_cast<uint32_t>(0)) + CONSTEXPR reset_r() : + pending_CPL(static_cast<uint32_t>(::privilege_level::USER)), + pending_CSL(static_cast<uint32_t>(::security_level::SECURE)), reserved0(static_cast<uint32_t>(0)) { } - CONSTEXPR dma_status0_r(uint32_t init) : word(init) {} + CONSTEXPR reset_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -2022,495 +1790,550 @@ struct dma_status0_r { return word; } - dma_status0_r copy() volatile + reset_r copy() volatile { return *this; } - CONSTEXPR uint32_t get_CMD_IDLE() const + CONSTEXPR ::privilege_level get_pending_CPL() const { - uint32_t value = static_cast<uint32_t>(CMD_IDLE); + ::privilege_level value = static_cast<::privilege_level>(pending_CPL); return value; } - uint32_t get_CMD_IDLE() const volatile + ::privilege_level get_pending_CPL() const volatile { - uint32_t value = static_cast<uint32_t>(CMD_IDLE); + ::privilege_level value = static_cast<::privilege_level>(pending_CPL); return value; } - CONSTEXPR dma_status0_r &set_CMD_IDLE(uint32_t value) + CONSTEXPR reset_r &set_pending_CPL(::privilege_level value) { - CMD_IDLE = ((1u << 1) - 1) & static_cast<uint32_t>(value); + pending_CPL = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IFM_IDLE() const + CONSTEXPR ::security_level get_pending_CSL() const { - uint32_t value = static_cast<uint32_t>(IFM_IDLE); + ::security_level value = static_cast<::security_level>(pending_CSL); return value; } - uint32_t get_IFM_IDLE() const volatile + ::security_level get_pending_CSL() const volatile { - uint32_t value = static_cast<uint32_t>(IFM_IDLE); + ::security_level value = static_cast<::security_level>(pending_CSL); return value; } - CONSTEXPR dma_status0_r &set_IFM_IDLE(uint32_t value) + CONSTEXPR reset_r &set_pending_CSL(::security_level value) { - IFM_IDLE = ((1u << 1) - 1) & static_cast<uint32_t>(value); + pending_CSL = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_WGT_IDLE_C0() const +#endif //__cplusplus +}; + +// qbase0_r - Base address of command queue bits [31:0]. The address is 4 byte aligned +struct qbase0_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - uint32_t value = static_cast<uint32_t>(WGT_IDLE_C0); - return value; - } - uint32_t get_WGT_IDLE_C0() const volatile + uint32_t QBASE0; // The 4 byte aligned lower bytes of the base address value for the command stream + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR qbase0_r() : QBASE0(static_cast<uint32_t>(0x00000000)) {} + CONSTEXPR qbase0_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(WGT_IDLE_C0); - return value; + word = value; } - CONSTEXPR dma_status0_r &set_WGT_IDLE_C0(uint32_t value) + void operator=(uint32_t value) volatile { - WGT_IDLE_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_BAS_IDLE_C0() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(BAS_IDLE_C0); - return value; + return word; } - uint32_t get_BAS_IDLE_C0() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(BAS_IDLE_C0); - return value; + return word; } - CONSTEXPR dma_status0_r &set_BAS_IDLE_C0(uint32_t value) + qbase0_r copy() volatile { - BAS_IDLE_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_M2M_IDLE() const + CONSTEXPR uint32_t get_QBASE0() const { - uint32_t value = static_cast<uint32_t>(M2M_IDLE); + uint32_t value = static_cast<uint32_t>(QBASE0); return value; } - uint32_t get_M2M_IDLE() const volatile + uint32_t get_QBASE0() const volatile { - uint32_t value = static_cast<uint32_t>(M2M_IDLE); + uint32_t value = static_cast<uint32_t>(QBASE0); return value; } - CONSTEXPR dma_status0_r &set_M2M_IDLE(uint32_t value) + CONSTEXPR qbase0_r &set_QBASE0(uint32_t value) { - M2M_IDLE = ((1u << 1) - 1) & static_cast<uint32_t>(value); + QBASE0 = static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_OFM_IDLE() const +#endif //__cplusplus +}; + +// qbase1_r - Address extension bits [47:32] bits for queue base +struct qbase1_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - uint32_t value = static_cast<uint32_t>(OFM_IDLE); - return value; - } - uint32_t get_OFM_IDLE() const volatile + uint32_t QBASE1; // The 4 byte aligned upper bytes of the base address value for the command stream + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR qbase1_r() : QBASE1(static_cast<uint32_t>(0x00000000)) {} + CONSTEXPR qbase1_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(OFM_IDLE); - return value; + word = value; } - CONSTEXPR dma_status0_r &set_OFM_IDLE(uint32_t value) + void operator=(uint32_t value) volatile { - OFM_IDLE = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_HALT_REQ() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(HALT_REQ); - return value; + return word; } - uint32_t get_HALT_REQ() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(HALT_REQ); - return value; + return word; } - CONSTEXPR dma_status0_r &set_HALT_REQ(uint32_t value) + qbase1_r copy() volatile { - HALT_REQ = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_HALT_ACK() const + CONSTEXPR uint32_t get_QBASE1() const { - uint32_t value = static_cast<uint32_t>(HALT_ACK); + uint32_t value = static_cast<uint32_t>(QBASE1); return value; } - uint32_t get_HALT_ACK() const volatile + uint32_t get_QBASE1() const volatile { - uint32_t value = static_cast<uint32_t>(HALT_ACK); + uint32_t value = static_cast<uint32_t>(QBASE1); return value; } - CONSTEXPR dma_status0_r &set_HALT_ACK(uint32_t value) + CONSTEXPR qbase1_r &set_QBASE1(uint32_t value) { - HALT_ACK = ((1u << 1) - 1) & static_cast<uint32_t>(value); + QBASE1 = static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_PAUSE_REQ() const +#endif //__cplusplus +}; + +// qread_r - Read offset in the command stream in bytes. Multiple of 4 in the range 0 to 16 MB +struct qread_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - uint32_t value = static_cast<uint32_t>(PAUSE_REQ); - return value; - } - uint32_t get_PAUSE_REQ() const volatile + uint32_t QREAD; // The read offset of the current command under execution + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR qread_r() : QREAD(static_cast<uint32_t>(0x00000000)) {} + CONSTEXPR qread_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(PAUSE_REQ); - return value; + word = value; } - CONSTEXPR dma_status0_r &set_PAUSE_REQ(uint32_t value) + void operator=(uint32_t value) volatile { - PAUSE_REQ = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_PAUSE_ACK() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(PAUSE_ACK); - return value; + return word; } - uint32_t get_PAUSE_ACK() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(PAUSE_ACK); - return value; + return word; } - CONSTEXPR dma_status0_r &set_PAUSE_ACK(uint32_t value) + qread_r copy() volatile { - PAUSE_ACK = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB0_AI_VALID_C0() const + CONSTEXPR uint32_t get_QREAD() const { - uint32_t value = static_cast<uint32_t>(IB0_AI_VALID_C0); + uint32_t value = static_cast<uint32_t>(QREAD); return value; } - uint32_t get_IB0_AI_VALID_C0() const volatile + uint32_t get_QREAD() const volatile { - uint32_t value = static_cast<uint32_t>(IB0_AI_VALID_C0); + uint32_t value = static_cast<uint32_t>(QREAD); return value; } - CONSTEXPR dma_status0_r &set_IB0_AI_VALID_C0(uint32_t value) + CONSTEXPR qread_r &set_QREAD(uint32_t value) { - IB0_AI_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + QREAD = static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB0_AI_READY_C0() const +#endif //__cplusplus +}; + +// qconfig_r - AXI configuration for the command stream in the range 0-3. Same encoding as for REGIONCFG +struct qconfig_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - uint32_t value = static_cast<uint32_t>(IB0_AI_READY_C0); - return value; - } - uint32_t get_IB0_AI_READY_C0() const volatile + uint32_t QCONFIG; // AXI configuration for the command stream in the range 0-3 + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR qconfig_r() : QCONFIG(static_cast<uint32_t>(0x00000000)) {} + CONSTEXPR qconfig_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(IB0_AI_READY_C0); - return value; + word = value; } - CONSTEXPR dma_status0_r &set_IB0_AI_READY_C0(uint32_t value) + void operator=(uint32_t value) volatile { - IB0_AI_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_IB1_AI_VALID_C0() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(IB1_AI_VALID_C0); - return value; + return word; } - uint32_t get_IB1_AI_VALID_C0() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(IB1_AI_VALID_C0); - return value; + return word; } - CONSTEXPR dma_status0_r &set_IB1_AI_VALID_C0(uint32_t value) + qconfig_r copy() volatile { - IB1_AI_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB1_AI_READY_C0() const + CONSTEXPR uint32_t get_QCONFIG() const { - uint32_t value = static_cast<uint32_t>(IB1_AI_READY_C0); + uint32_t value = static_cast<uint32_t>(QCONFIG); return value; } - uint32_t get_IB1_AI_READY_C0() const volatile + uint32_t get_QCONFIG() const volatile { - uint32_t value = static_cast<uint32_t>(IB1_AI_READY_C0); + uint32_t value = static_cast<uint32_t>(QCONFIG); return value; } - CONSTEXPR dma_status0_r &set_IB1_AI_READY_C0(uint32_t value) + CONSTEXPR qconfig_r &set_QCONFIG(uint32_t value) { - IB1_AI_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + QCONFIG = static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB0_AO_VALID_C0() const +#endif //__cplusplus +}; + +// qsize_r - Size of the command stream in bytes. Multiple of 4 in the range 0 to 16 MB +struct qsize_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - uint32_t value = static_cast<uint32_t>(IB0_AO_VALID_C0); - return value; - } - uint32_t get_IB0_AO_VALID_C0() const volatile + uint32_t QSIZE; // Size of the next command stream to be executed by the NPU + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR qsize_r() : QSIZE(static_cast<uint32_t>(0x00000000)) {} + CONSTEXPR qsize_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(IB0_AO_VALID_C0); - return value; + word = value; } - CONSTEXPR dma_status0_r &set_IB0_AO_VALID_C0(uint32_t value) + void operator=(uint32_t value) volatile { - IB0_AO_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_IB0_AO_READY_C0() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(IB0_AO_READY_C0); - return value; + return word; } - uint32_t get_IB0_AO_READY_C0() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(IB0_AO_READY_C0); - return value; + return word; } - CONSTEXPR dma_status0_r &set_IB0_AO_READY_C0(uint32_t value) + qsize_r copy() volatile { - IB0_AO_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB1_AO_VALID_C0() const + CONSTEXPR uint32_t get_QSIZE() const { - uint32_t value = static_cast<uint32_t>(IB1_AO_VALID_C0); + uint32_t value = static_cast<uint32_t>(QSIZE); return value; } - uint32_t get_IB1_AO_VALID_C0() const volatile + uint32_t get_QSIZE() const volatile { - uint32_t value = static_cast<uint32_t>(IB1_AO_VALID_C0); + uint32_t value = static_cast<uint32_t>(QSIZE); return value; } - CONSTEXPR dma_status0_r &set_IB1_AO_VALID_C0(uint32_t value) + CONSTEXPR qsize_r &set_QSIZE(uint32_t value) { - IB1_AO_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + QSIZE = static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB1_AO_READY_C0() const - { - uint32_t value = static_cast<uint32_t>(IB1_AO_READY_C0); - return value; - } - uint32_t get_IB1_AO_READY_C0() const volatile - { - uint32_t value = static_cast<uint32_t>(IB1_AO_READY_C0); - return value; - } - CONSTEXPR dma_status0_r &set_IB1_AO_READY_C0(uint32_t value) +#endif //__cplusplus +}; + +// prot_r - Protection level configured for the NPU when acting as an AXI master +struct prot_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - IB1_AO_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_OB0_VALID_C0() const + struct + { + uint32_t active_CPL : 1; // Current privilege level 0=User 1=Privileged + uint32_t active_CSL : 1; // Current security level 0=Secure 1=Non secure + uint32_t reserved0 : 30; + }; + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR prot_r() : + active_CPL(static_cast<uint32_t>(::privilege_level::USER)), + active_CSL(static_cast<uint32_t>(::security_level::SECURE)), reserved0(static_cast<uint32_t>(0)) { - uint32_t value = static_cast<uint32_t>(OB0_VALID_C0); - return value; } - uint32_t get_OB0_VALID_C0() const volatile + CONSTEXPR prot_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(OB0_VALID_C0); - return value; + word = value; } - CONSTEXPR dma_status0_r &set_OB0_VALID_C0(uint32_t value) + void operator=(uint32_t value) volatile { - OB0_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_OB0_READY_C0() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(OB0_READY_C0); - return value; + return word; } - uint32_t get_OB0_READY_C0() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(OB0_READY_C0); - return value; + return word; } - CONSTEXPR dma_status0_r &set_OB0_READY_C0(uint32_t value) + prot_r copy() volatile { - OB0_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_OB1_VALID_C0() const + CONSTEXPR ::privilege_level get_active_CPL() const { - uint32_t value = static_cast<uint32_t>(OB1_VALID_C0); + ::privilege_level value = static_cast<::privilege_level>(active_CPL); return value; } - uint32_t get_OB1_VALID_C0() const volatile + ::privilege_level get_active_CPL() const volatile { - uint32_t value = static_cast<uint32_t>(OB1_VALID_C0); + ::privilege_level value = static_cast<::privilege_level>(active_CPL); return value; } - CONSTEXPR dma_status0_r &set_OB1_VALID_C0(uint32_t value) + CONSTEXPR prot_r &set_active_CPL(::privilege_level value) { - OB1_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + active_CPL = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_OB1_READY_C0() const + CONSTEXPR ::security_level get_active_CSL() const { - uint32_t value = static_cast<uint32_t>(OB1_READY_C0); + ::security_level value = static_cast<::security_level>(active_CSL); return value; } - uint32_t get_OB1_READY_C0() const volatile + ::security_level get_active_CSL() const volatile { - uint32_t value = static_cast<uint32_t>(OB1_READY_C0); + ::security_level value = static_cast<::security_level>(active_CSL); return value; } - CONSTEXPR dma_status0_r &set_OB1_READY_C0(uint32_t value) + CONSTEXPR prot_r &set_active_CSL(::security_level value) { - OB1_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + active_CSL = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_CMD_VALID() const - { - uint32_t value = static_cast<uint32_t>(CMD_VALID); - return value; - } - uint32_t get_CMD_VALID() const volatile - { - uint32_t value = static_cast<uint32_t>(CMD_VALID); - return value; - } - CONSTEXPR dma_status0_r &set_CMD_VALID(uint32_t value) +#endif //__cplusplus +}; + +// config_r - RTL configuration +struct config_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - CMD_VALID = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_CMD_READY() const + struct + { + uint32_t macs_per_cc : 4; // The log2(macs/clock cycle). Valid encoding range is 5 to 8 for 32 to 256 + // MACs/clock cycle. + uint32_t cmd_stream_version : 4; // command stream version accepted by this NPU. Set to 0 for Ethos-U55 EAC. + uint32_t shram_size : 8; // Size in KB of SHRAM in the range 8 to 48. + uint32_t reserved0 : 12; + uint32_t product : 4; // Product configuration + }; + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR config_r() : + macs_per_cc(static_cast<uint32_t>(0)), cmd_stream_version(static_cast<uint32_t>(0x0)), + shram_size(static_cast<uint32_t>(0)), reserved0(static_cast<uint32_t>(0)), product(static_cast<uint32_t>(0)) { - uint32_t value = static_cast<uint32_t>(CMD_READY); - return value; } - uint32_t get_CMD_READY() const volatile + CONSTEXPR config_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(CMD_READY); - return value; + word = value; } - CONSTEXPR dma_status0_r &set_CMD_READY(uint32_t value) + void operator=(uint32_t value) volatile { - CMD_READY = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_WD_BITSTREAM_VALID_C0() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_VALID_C0); - return value; + return word; } - uint32_t get_WD_BITSTREAM_VALID_C0() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_VALID_C0); - return value; + return word; } - CONSTEXPR dma_status0_r &set_WD_BITSTREAM_VALID_C0(uint32_t value) + config_r copy() volatile { - WD_BITSTREAM_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_WD_BITSTREAM_READY_C0() const + CONSTEXPR ::macs_per_cc get_macs_per_cc() const { - uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_READY_C0); + ::macs_per_cc value = static_cast<::macs_per_cc>(macs_per_cc); return value; } - uint32_t get_WD_BITSTREAM_READY_C0() const volatile + ::macs_per_cc get_macs_per_cc() const volatile { - uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_READY_C0); + ::macs_per_cc value = static_cast<::macs_per_cc>(macs_per_cc); return value; } - CONSTEXPR dma_status0_r &set_WD_BITSTREAM_READY_C0(uint32_t value) + CONSTEXPR config_r &set_macs_per_cc(::macs_per_cc value) { - WD_BITSTREAM_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + macs_per_cc = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_BS_BITSTREAM_VALID_C0() const + CONSTEXPR uint32_t get_cmd_stream_version() const { - uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_VALID_C0); + uint32_t value = static_cast<uint32_t>(cmd_stream_version); return value; } - uint32_t get_BS_BITSTREAM_VALID_C0() const volatile + uint32_t get_cmd_stream_version() const volatile { - uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_VALID_C0); + uint32_t value = static_cast<uint32_t>(cmd_stream_version); return value; } - CONSTEXPR dma_status0_r &set_BS_BITSTREAM_VALID_C0(uint32_t value) + CONSTEXPR config_r &set_cmd_stream_version(uint32_t value) { - BS_BITSTREAM_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + cmd_stream_version = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_BS_BITSTREAM_READY_C0() const + CONSTEXPR ::shram_size get_shram_size() const { - uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_READY_C0); + ::shram_size value = static_cast<::shram_size>(shram_size); return value; } - uint32_t get_BS_BITSTREAM_READY_C0() const volatile + ::shram_size get_shram_size() const volatile { - uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_READY_C0); + ::shram_size value = static_cast<::shram_size>(shram_size); return value; } - CONSTEXPR dma_status0_r &set_BS_BITSTREAM_READY_C0(uint32_t value) + CONSTEXPR config_r &set_shram_size(::shram_size value) { - BS_BITSTREAM_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + shram_size = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_AXI0_AR_STALLED() const + CONSTEXPR uint32_t get_product() const { - uint32_t value = static_cast<uint32_t>(AXI0_AR_STALLED); + uint32_t value = static_cast<uint32_t>(product); return value; } - uint32_t get_AXI0_AR_STALLED() const volatile + uint32_t get_product() const volatile { - uint32_t value = static_cast<uint32_t>(AXI0_AR_STALLED); + uint32_t value = static_cast<uint32_t>(product); return value; } - CONSTEXPR dma_status0_r &set_AXI0_AR_STALLED(uint32_t value) + CONSTEXPR config_r &set_product(uint32_t value) { - AXI0_AR_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); + product = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_AXI0_RD_LIMIT_STALL() const +#endif //__cplusplus +}; + +// lock_r - Lock register. This register is designed for driver use and does not affect NPU functionality +struct lock_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - uint32_t value = static_cast<uint32_t>(AXI0_RD_LIMIT_STALL); - return value; - } - uint32_t get_AXI0_RD_LIMIT_STALL() const volatile + uint32_t LOCK; // 32 bit value for LOCK configuration + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR lock_r() : LOCK(static_cast<uint32_t>(0x00000000)) {} + CONSTEXPR lock_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(AXI0_RD_LIMIT_STALL); - return value; + word = value; } - CONSTEXPR dma_status0_r &set_AXI0_RD_LIMIT_STALL(uint32_t value) + void operator=(uint32_t value) volatile { - AXI0_RD_LIMIT_STALL = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_AXI0_AW_STALLED() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(AXI0_AW_STALLED); - return value; + return word; } - uint32_t get_AXI0_AW_STALLED() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(AXI0_AW_STALLED); - return value; + return word; } - CONSTEXPR dma_status0_r &set_AXI0_AW_STALLED(uint32_t value) + lock_r copy() volatile { - AXI0_AW_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_AXI0_W_STALLED() const + CONSTEXPR uint32_t get_LOCK() const { - uint32_t value = static_cast<uint32_t>(AXI0_W_STALLED); + uint32_t value = static_cast<uint32_t>(LOCK); return value; } - uint32_t get_AXI0_W_STALLED() const volatile + uint32_t get_LOCK() const volatile { - uint32_t value = static_cast<uint32_t>(AXI0_W_STALLED); + uint32_t value = static_cast<uint32_t>(LOCK); return value; } - CONSTEXPR dma_status0_r &set_AXI0_W_STALLED(uint32_t value) + CONSTEXPR lock_r &set_LOCK(uint32_t value) { - AXI0_W_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); + LOCK = static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// dma_status1_r - DMA_STATUS1 of core DEBUGCORE -struct dma_status1_r +// regioncfg_r - Base pointer configuration. Bits[2*k+1:2*k] give the memory type for REGION[k] +struct regioncfg_r { #ifdef __cplusplus private: @@ -2519,55 +2342,32 @@ struct dma_status1_r { struct { - uint32_t AXI0_WR_LIMIT_STALL : 1; // Write stalled due to one AXI0 limit counter being reached - uint32_t AXI1_AR_STALLED : 1; // Read transfer request stalled on arready low AXI1 (due to memory system) - uint32_t AXI1_RD_LIMIT_STALL : 1; // Read stalled due to one AXI1 limit counter being reached - uint32_t AXI1_WR_STALLED : 1; // Write transfer request stalled on awready low AXI1 (due to memory system) - uint32_t AXI1_W_STALLED : 1; // Write transfer stalled on wready low AXI1 (due to memory system) - uint32_t AXI1_WR_LIMIT_STALL : 1; // Write stalled due to one AXI1 limit counter being reached - uint32_t WGT_IDLE_C1 : 1; // When this bit is high means that the WGT block is not busy in generating - // addresses for a WGT job - uint32_t BAS_IDLE_C1 : 1; // When this bit is high means that the BAS block is not busy in generating - // addresses for a BAS job. - uint32_t IB0_AI_VALID_C1 : 1; // Data for AI to be read in IFM input buffer 0 - Core 1 - uint32_t IB0_AI_READY_C1 : 1; // Data consumed from AI in IFM input buffer 0 - Core 1 - uint32_t IB1_AI_VALID_C1 : 1; // Data for AI to be read in IFM input buffer 1 - Core 1 - uint32_t IB1_AI_READY_C1 : 1; // Data consumed from AI in IFM input buffer 1 - Core 1 - uint32_t IB0_AO_VALID_C1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1 - uint32_t IB0_AO_READY_C1 : 1; // Data consumed from AO in IFM input buffer 0 - Core 1 - uint32_t IB1_AO_VALID_C1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1 - uint32_t IB1_AO_READY_C1 : 1; // Data consumed from AO in IFM input buffer 1 - Core 1 - uint32_t OB0_VALID_C1 : 1; // Data for DMA ready to be consumed in OFM output buffer 0 - Core 1 - uint32_t OB0_READY_C1 : 1; // Data consumed from DMA in OFM output buffer 0 - Core 1 - uint32_t OB1_VALID_C1 : 1; // Data for DMA ready to be consumed in OFM output buffer 1 - Core 1 - uint32_t OB1_READY_C1 : 1; // Data consumed from DMA in OFM output buffer 1 - Core 1 - uint32_t WD_BITSTREAM_VALID_C1 : 1; // New weight word for WD to be consumed - Core 1 - uint32_t WD_BITSTREAM_READY_C1 : 1; // Weight word consumed by WD - Core 1 - uint32_t BS_BITSTREAM_VALID_C1 : 1; // New BaS word for AO to be consumed - Core 1 - uint32_t BS_BITSTREAM_READY_C1 : 1; // BaS word consumed by AO - Core 1 - uint32_t reserved0 : 8; + uint32_t region0 : 2; // Bits for Region0 Configurion + uint32_t region1 : 2; // Bits for Region1 Configurion + uint32_t region2 : 2; // Bits for Region2 Configurion + uint32_t region3 : 2; // Bits for Region3 Configurion + uint32_t region4 : 2; // Bits for Region4 Configurion + uint32_t region5 : 2; // Bits for Region5 Configurion + uint32_t region6 : 2; // Bits for Region6 Configurion + uint32_t region7 : 2; // Bits for Region7 Configurion + uint32_t reserved0 : 16; }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR dma_status1_r() : - AXI0_WR_LIMIT_STALL(static_cast<uint32_t>(0)), AXI1_AR_STALLED(static_cast<uint32_t>(0)), - AXI1_RD_LIMIT_STALL(static_cast<uint32_t>(0)), AXI1_WR_STALLED(static_cast<uint32_t>(0)), - AXI1_W_STALLED(static_cast<uint32_t>(0)), AXI1_WR_LIMIT_STALL(static_cast<uint32_t>(0)), - WGT_IDLE_C1(static_cast<uint32_t>(0)), BAS_IDLE_C1(static_cast<uint32_t>(0)), - IB0_AI_VALID_C1(static_cast<uint32_t>(0)), IB0_AI_READY_C1(static_cast<uint32_t>(0)), - IB1_AI_VALID_C1(static_cast<uint32_t>(0)), IB1_AI_READY_C1(static_cast<uint32_t>(0)), - IB0_AO_VALID_C1(static_cast<uint32_t>(0)), IB0_AO_READY_C1(static_cast<uint32_t>(0)), - IB1_AO_VALID_C1(static_cast<uint32_t>(0)), IB1_AO_READY_C1(static_cast<uint32_t>(0)), - OB0_VALID_C1(static_cast<uint32_t>(0)), OB0_READY_C1(static_cast<uint32_t>(0)), - OB1_VALID_C1(static_cast<uint32_t>(0)), OB1_READY_C1(static_cast<uint32_t>(0)), - WD_BITSTREAM_VALID_C1(static_cast<uint32_t>(0)), WD_BITSTREAM_READY_C1(static_cast<uint32_t>(0)), - BS_BITSTREAM_VALID_C1(static_cast<uint32_t>(0)), BS_BITSTREAM_READY_C1(static_cast<uint32_t>(0)), - reserved0(static_cast<uint32_t>(0)) + CONSTEXPR regioncfg_r() : + region0(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), + region1(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), + region2(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), + region3(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), + region4(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), + region5(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), + region6(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), + region7(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), reserved0(static_cast<uint32_t>(0)) { } - CONSTEXPR dma_status1_r(uint32_t init) : word(init) {} + CONSTEXPR regioncfg_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -2584,375 +2384,474 @@ struct dma_status1_r { return word; } - dma_status1_r copy() volatile + regioncfg_r copy() volatile { return *this; } - CONSTEXPR uint32_t get_AXI0_WR_LIMIT_STALL() const + CONSTEXPR ::memory_type get_region0() const { - uint32_t value = static_cast<uint32_t>(AXI0_WR_LIMIT_STALL); + ::memory_type value = static_cast<::memory_type>(region0); return value; } - uint32_t get_AXI0_WR_LIMIT_STALL() const volatile + ::memory_type get_region0() const volatile { - uint32_t value = static_cast<uint32_t>(AXI0_WR_LIMIT_STALL); + ::memory_type value = static_cast<::memory_type>(region0); return value; } - CONSTEXPR dma_status1_r &set_AXI0_WR_LIMIT_STALL(uint32_t value) + CONSTEXPR regioncfg_r &set_region0(::memory_type value) { - AXI0_WR_LIMIT_STALL = ((1u << 1) - 1) & static_cast<uint32_t>(value); + region0 = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_AXI1_AR_STALLED() const + CONSTEXPR ::memory_type get_region1() const { - uint32_t value = static_cast<uint32_t>(AXI1_AR_STALLED); + ::memory_type value = static_cast<::memory_type>(region1); return value; } - uint32_t get_AXI1_AR_STALLED() const volatile + ::memory_type get_region1() const volatile { - uint32_t value = static_cast<uint32_t>(AXI1_AR_STALLED); + ::memory_type value = static_cast<::memory_type>(region1); return value; } - CONSTEXPR dma_status1_r &set_AXI1_AR_STALLED(uint32_t value) + CONSTEXPR regioncfg_r &set_region1(::memory_type value) { - AXI1_AR_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); + region1 = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_AXI1_RD_LIMIT_STALL() const + CONSTEXPR ::memory_type get_region2() const { - uint32_t value = static_cast<uint32_t>(AXI1_RD_LIMIT_STALL); + ::memory_type value = static_cast<::memory_type>(region2); return value; } - uint32_t get_AXI1_RD_LIMIT_STALL() const volatile + ::memory_type get_region2() const volatile { - uint32_t value = static_cast<uint32_t>(AXI1_RD_LIMIT_STALL); + ::memory_type value = static_cast<::memory_type>(region2); return value; } - CONSTEXPR dma_status1_r &set_AXI1_RD_LIMIT_STALL(uint32_t value) + CONSTEXPR regioncfg_r &set_region2(::memory_type value) { - AXI1_RD_LIMIT_STALL = ((1u << 1) - 1) & static_cast<uint32_t>(value); + region2 = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_AXI1_WR_STALLED() const + CONSTEXPR ::memory_type get_region3() const { - uint32_t value = static_cast<uint32_t>(AXI1_WR_STALLED); + ::memory_type value = static_cast<::memory_type>(region3); return value; } - uint32_t get_AXI1_WR_STALLED() const volatile + ::memory_type get_region3() const volatile { - uint32_t value = static_cast<uint32_t>(AXI1_WR_STALLED); + ::memory_type value = static_cast<::memory_type>(region3); return value; } - CONSTEXPR dma_status1_r &set_AXI1_WR_STALLED(uint32_t value) + CONSTEXPR regioncfg_r &set_region3(::memory_type value) { - AXI1_WR_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); + region3 = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_AXI1_W_STALLED() const + CONSTEXPR ::memory_type get_region4() const { - uint32_t value = static_cast<uint32_t>(AXI1_W_STALLED); + ::memory_type value = static_cast<::memory_type>(region4); return value; } - uint32_t get_AXI1_W_STALLED() const volatile + ::memory_type get_region4() const volatile { - uint32_t value = static_cast<uint32_t>(AXI1_W_STALLED); + ::memory_type value = static_cast<::memory_type>(region4); return value; } - CONSTEXPR dma_status1_r &set_AXI1_W_STALLED(uint32_t value) + CONSTEXPR regioncfg_r &set_region4(::memory_type value) { - AXI1_W_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); + region4 = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_AXI1_WR_LIMIT_STALL() const + CONSTEXPR ::memory_type get_region5() const { - uint32_t value = static_cast<uint32_t>(AXI1_WR_LIMIT_STALL); + ::memory_type value = static_cast<::memory_type>(region5); return value; } - uint32_t get_AXI1_WR_LIMIT_STALL() const volatile + ::memory_type get_region5() const volatile { - uint32_t value = static_cast<uint32_t>(AXI1_WR_LIMIT_STALL); + ::memory_type value = static_cast<::memory_type>(region5); return value; } - CONSTEXPR dma_status1_r &set_AXI1_WR_LIMIT_STALL(uint32_t value) + CONSTEXPR regioncfg_r &set_region5(::memory_type value) { - AXI1_WR_LIMIT_STALL = ((1u << 1) - 1) & static_cast<uint32_t>(value); + region5 = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_WGT_IDLE_C1() const + CONSTEXPR ::memory_type get_region6() const { - uint32_t value = static_cast<uint32_t>(WGT_IDLE_C1); + ::memory_type value = static_cast<::memory_type>(region6); return value; } - uint32_t get_WGT_IDLE_C1() const volatile + ::memory_type get_region6() const volatile { - uint32_t value = static_cast<uint32_t>(WGT_IDLE_C1); + ::memory_type value = static_cast<::memory_type>(region6); return value; } - CONSTEXPR dma_status1_r &set_WGT_IDLE_C1(uint32_t value) + CONSTEXPR regioncfg_r &set_region6(::memory_type value) { - WGT_IDLE_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + region6 = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_BAS_IDLE_C1() const + CONSTEXPR ::memory_type get_region7() const { - uint32_t value = static_cast<uint32_t>(BAS_IDLE_C1); + ::memory_type value = static_cast<::memory_type>(region7); return value; } - uint32_t get_BAS_IDLE_C1() const volatile + ::memory_type get_region7() const volatile { - uint32_t value = static_cast<uint32_t>(BAS_IDLE_C1); + ::memory_type value = static_cast<::memory_type>(region7); return value; } - CONSTEXPR dma_status1_r &set_BAS_IDLE_C1(uint32_t value) + CONSTEXPR regioncfg_r &set_region7(::memory_type value) { - BAS_IDLE_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + region7 = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB0_AI_VALID_C1() const +#endif //__cplusplus +}; + +// axi_limit0_r - AXI limits for port 0 counter 0 +struct axi_limit0_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union + { + struct + { + uint32_t max_beats : 2; // Burst split alignment: 0=64 bytes, 1=128 bytes, 2=256 bytes, 3=reserved + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 8; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 + uint32_t max_outstanding_write_m1 : 8; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 15 + }; + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR axi_limit0_r() : + max_beats(static_cast<uint32_t>(0x0)), reserved0(static_cast<uint32_t>(0)), memtype(static_cast<uint32_t>(0)), + reserved1(static_cast<uint32_t>(0)), max_outstanding_read_m1(static_cast<uint32_t>(0x00)), + max_outstanding_write_m1(static_cast<uint32_t>(0x00)) { - uint32_t value = static_cast<uint32_t>(IB0_AI_VALID_C1); - return value; } - uint32_t get_IB0_AI_VALID_C1() const volatile + CONSTEXPR axi_limit0_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(IB0_AI_VALID_C1); - return value; + word = value; } - CONSTEXPR dma_status1_r &set_IB0_AI_VALID_C1(uint32_t value) + void operator=(uint32_t value) volatile { - IB0_AI_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_IB0_AI_READY_C1() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(IB0_AI_READY_C1); - return value; + return word; } - uint32_t get_IB0_AI_READY_C1() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(IB0_AI_READY_C1); - return value; + return word; } - CONSTEXPR dma_status1_r &set_IB0_AI_READY_C1(uint32_t value) + axi_limit0_r copy() volatile { - IB0_AI_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB1_AI_VALID_C1() const + CONSTEXPR uint32_t get_max_beats() const { - uint32_t value = static_cast<uint32_t>(IB1_AI_VALID_C1); + uint32_t value = static_cast<uint32_t>(max_beats); return value; } - uint32_t get_IB1_AI_VALID_C1() const volatile + uint32_t get_max_beats() const volatile { - uint32_t value = static_cast<uint32_t>(IB1_AI_VALID_C1); + uint32_t value = static_cast<uint32_t>(max_beats); return value; } - CONSTEXPR dma_status1_r &set_IB1_AI_VALID_C1(uint32_t value) + CONSTEXPR axi_limit0_r &set_max_beats(uint32_t value) { - IB1_AI_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_beats = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB1_AI_READY_C1() const + CONSTEXPR uint32_t get_memtype() const { - uint32_t value = static_cast<uint32_t>(IB1_AI_READY_C1); + uint32_t value = static_cast<uint32_t>(memtype); return value; } - uint32_t get_IB1_AI_READY_C1() const volatile + uint32_t get_memtype() const volatile { - uint32_t value = static_cast<uint32_t>(IB1_AI_READY_C1); + uint32_t value = static_cast<uint32_t>(memtype); return value; } - CONSTEXPR dma_status1_r &set_IB1_AI_READY_C1(uint32_t value) + CONSTEXPR axi_limit0_r &set_memtype(uint32_t value) { - IB1_AI_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + memtype = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB0_AO_VALID_C1() const + CONSTEXPR uint32_t get_max_outstanding_read_m1() const { - uint32_t value = static_cast<uint32_t>(IB0_AO_VALID_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); return value; } - uint32_t get_IB0_AO_VALID_C1() const volatile + uint32_t get_max_outstanding_read_m1() const volatile { - uint32_t value = static_cast<uint32_t>(IB0_AO_VALID_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); return value; } - CONSTEXPR dma_status1_r &set_IB0_AO_VALID_C1(uint32_t value) + CONSTEXPR axi_limit0_r &set_max_outstanding_read_m1(uint32_t value) { - IB0_AO_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_outstanding_read_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB0_AO_READY_C1() const + CONSTEXPR uint32_t get_max_outstanding_write_m1() const { - uint32_t value = static_cast<uint32_t>(IB0_AO_READY_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); return value; } - uint32_t get_IB0_AO_READY_C1() const volatile + uint32_t get_max_outstanding_write_m1() const volatile { - uint32_t value = static_cast<uint32_t>(IB0_AO_READY_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); return value; } - CONSTEXPR dma_status1_r &set_IB0_AO_READY_C1(uint32_t value) + CONSTEXPR axi_limit0_r &set_max_outstanding_write_m1(uint32_t value) { - IB0_AO_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_outstanding_write_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB1_AO_VALID_C1() const +#endif //__cplusplus +}; + +// axi_limit1_r - AXI limits for port 0 counter 1 +struct axi_limit1_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union + { + struct + { + uint32_t max_beats : 2; // Burst split alignment: 0=64 bytes, 1=128 bytes, 2=256 bytes, 3=reserved + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 8; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 + uint32_t max_outstanding_write_m1 : 8; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 15 + }; + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR axi_limit1_r() : + max_beats(static_cast<uint32_t>(0x0)), reserved0(static_cast<uint32_t>(0)), memtype(static_cast<uint32_t>(0)), + reserved1(static_cast<uint32_t>(0)), max_outstanding_read_m1(static_cast<uint32_t>(0x00)), + max_outstanding_write_m1(static_cast<uint32_t>(0x00)) { - uint32_t value = static_cast<uint32_t>(IB1_AO_VALID_C1); - return value; } - uint32_t get_IB1_AO_VALID_C1() const volatile + CONSTEXPR axi_limit1_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(IB1_AO_VALID_C1); - return value; + word = value; } - CONSTEXPR dma_status1_r &set_IB1_AO_VALID_C1(uint32_t value) + void operator=(uint32_t value) volatile + { + word = value; + } + CONSTEXPR operator uint32_t() + { + return word; + } + operator uint32_t() volatile + { + return word; + } + axi_limit1_r copy() volatile { - IB1_AO_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_IB1_AO_READY_C1() const + CONSTEXPR uint32_t get_max_beats() const { - uint32_t value = static_cast<uint32_t>(IB1_AO_READY_C1); + uint32_t value = static_cast<uint32_t>(max_beats); return value; } - uint32_t get_IB1_AO_READY_C1() const volatile + uint32_t get_max_beats() const volatile { - uint32_t value = static_cast<uint32_t>(IB1_AO_READY_C1); + uint32_t value = static_cast<uint32_t>(max_beats); return value; } - CONSTEXPR dma_status1_r &set_IB1_AO_READY_C1(uint32_t value) + CONSTEXPR axi_limit1_r &set_max_beats(uint32_t value) { - IB1_AO_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_beats = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_OB0_VALID_C1() const + CONSTEXPR uint32_t get_memtype() const { - uint32_t value = static_cast<uint32_t>(OB0_VALID_C1); + uint32_t value = static_cast<uint32_t>(memtype); return value; } - uint32_t get_OB0_VALID_C1() const volatile + uint32_t get_memtype() const volatile { - uint32_t value = static_cast<uint32_t>(OB0_VALID_C1); + uint32_t value = static_cast<uint32_t>(memtype); return value; } - CONSTEXPR dma_status1_r &set_OB0_VALID_C1(uint32_t value) + CONSTEXPR axi_limit1_r &set_memtype(uint32_t value) { - OB0_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + memtype = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_OB0_READY_C1() const + CONSTEXPR uint32_t get_max_outstanding_read_m1() const { - uint32_t value = static_cast<uint32_t>(OB0_READY_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); return value; } - uint32_t get_OB0_READY_C1() const volatile + uint32_t get_max_outstanding_read_m1() const volatile { - uint32_t value = static_cast<uint32_t>(OB0_READY_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); return value; } - CONSTEXPR dma_status1_r &set_OB0_READY_C1(uint32_t value) + CONSTEXPR axi_limit1_r &set_max_outstanding_read_m1(uint32_t value) { - OB0_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_outstanding_read_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_OB1_VALID_C1() const + CONSTEXPR uint32_t get_max_outstanding_write_m1() const { - uint32_t value = static_cast<uint32_t>(OB1_VALID_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); return value; } - uint32_t get_OB1_VALID_C1() const volatile + uint32_t get_max_outstanding_write_m1() const volatile { - uint32_t value = static_cast<uint32_t>(OB1_VALID_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); return value; } - CONSTEXPR dma_status1_r &set_OB1_VALID_C1(uint32_t value) + CONSTEXPR axi_limit1_r &set_max_outstanding_write_m1(uint32_t value) { - OB1_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_outstanding_write_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_OB1_READY_C1() const +#endif //__cplusplus +}; + +// axi_limit2_r - AXI limits for port 1 counter 2 +struct axi_limit2_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union + { + struct + { + uint32_t max_beats : 2; // Burst split alignment: 0=64 bytes, 1=128 bytes, 2=256 bytes, 3=reserved + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 8; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 + uint32_t max_outstanding_write_m1 : 8; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 15 + }; + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR axi_limit2_r() : + max_beats(static_cast<uint32_t>(0x0)), reserved0(static_cast<uint32_t>(0)), memtype(static_cast<uint32_t>(0)), + reserved1(static_cast<uint32_t>(0)), max_outstanding_read_m1(static_cast<uint32_t>(0x00)), + max_outstanding_write_m1(static_cast<uint32_t>(0x00)) { - uint32_t value = static_cast<uint32_t>(OB1_READY_C1); - return value; } - uint32_t get_OB1_READY_C1() const volatile + CONSTEXPR axi_limit2_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(OB1_READY_C1); - return value; + word = value; } - CONSTEXPR dma_status1_r &set_OB1_READY_C1(uint32_t value) + void operator=(uint32_t value) volatile + { + word = value; + } + CONSTEXPR operator uint32_t() + { + return word; + } + operator uint32_t() volatile + { + return word; + } + axi_limit2_r copy() volatile { - OB1_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_WD_BITSTREAM_VALID_C1() const + CONSTEXPR uint32_t get_max_beats() const { - uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_VALID_C1); + uint32_t value = static_cast<uint32_t>(max_beats); return value; } - uint32_t get_WD_BITSTREAM_VALID_C1() const volatile + uint32_t get_max_beats() const volatile { - uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_VALID_C1); + uint32_t value = static_cast<uint32_t>(max_beats); return value; } - CONSTEXPR dma_status1_r &set_WD_BITSTREAM_VALID_C1(uint32_t value) + CONSTEXPR axi_limit2_r &set_max_beats(uint32_t value) { - WD_BITSTREAM_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_beats = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_WD_BITSTREAM_READY_C1() const + CONSTEXPR uint32_t get_memtype() const { - uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_READY_C1); + uint32_t value = static_cast<uint32_t>(memtype); return value; } - uint32_t get_WD_BITSTREAM_READY_C1() const volatile + uint32_t get_memtype() const volatile { - uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_READY_C1); + uint32_t value = static_cast<uint32_t>(memtype); return value; } - CONSTEXPR dma_status1_r &set_WD_BITSTREAM_READY_C1(uint32_t value) + CONSTEXPR axi_limit2_r &set_memtype(uint32_t value) { - WD_BITSTREAM_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + memtype = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_BS_BITSTREAM_VALID_C1() const + CONSTEXPR uint32_t get_max_outstanding_read_m1() const { - uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_VALID_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); return value; } - uint32_t get_BS_BITSTREAM_VALID_C1() const volatile + uint32_t get_max_outstanding_read_m1() const volatile { - uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_VALID_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); return value; } - CONSTEXPR dma_status1_r &set_BS_BITSTREAM_VALID_C1(uint32_t value) + CONSTEXPR axi_limit2_r &set_max_outstanding_read_m1(uint32_t value) { - BS_BITSTREAM_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_outstanding_read_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_BS_BITSTREAM_READY_C1() const + CONSTEXPR uint32_t get_max_outstanding_write_m1() const { - uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_READY_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); return value; } - uint32_t get_BS_BITSTREAM_READY_C1() const volatile + uint32_t get_max_outstanding_write_m1() const volatile { - uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_READY_C1); + uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); return value; } - CONSTEXPR dma_status1_r &set_BS_BITSTREAM_READY_C1(uint32_t value) + CONSTEXPR axi_limit2_r &set_max_outstanding_write_m1(uint32_t value) { - BS_BITSTREAM_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_outstanding_write_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// clkforce_r - Force clocks on for clock gating -struct clkforce_r +// axi_limit3_r - AXI limits for port 1 counter 3 +struct axi_limit3_r { #ifdef __cplusplus private: @@ -2961,25 +2860,26 @@ struct clkforce_r { struct { - uint32_t top_level_clk : 1; // set to 1 to force on TOP level clock - uint32_t cc_clk : 1; // set to 1 to force on CC clock - uint32_t dma_clk : 1; // set to 1 to force on DMA clock - uint32_t mac_clk : 1; // set to 1 to force on MAC clock - uint32_t ao_clk : 1; // set to 1 to force on AO clock - uint32_t wd_clk : 1; // set to 1 to force on WD clock - uint32_t reserved0 : 26; + uint32_t max_beats : 2; // Burst split alignment: 0=64 bytes, 1=128 bytes, 2=256 bytes, 3=reserved + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 8; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 + uint32_t max_outstanding_write_m1 : 8; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 15 }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR clkforce_r() : - top_level_clk(static_cast<uint32_t>(0)), cc_clk(static_cast<uint32_t>(0)), dma_clk(static_cast<uint32_t>(0)), - mac_clk(static_cast<uint32_t>(0)), ao_clk(static_cast<uint32_t>(0)), wd_clk(static_cast<uint32_t>(0)), - reserved0(static_cast<uint32_t>(0)) + CONSTEXPR axi_limit3_r() : + max_beats(static_cast<uint32_t>(0x0)), reserved0(static_cast<uint32_t>(0)), memtype(static_cast<uint32_t>(0)), + reserved1(static_cast<uint32_t>(0)), max_outstanding_read_m1(static_cast<uint32_t>(0x00)), + max_outstanding_write_m1(static_cast<uint32_t>(0x00)) { } - CONSTEXPR clkforce_r(uint32_t init) : word(init) {} + CONSTEXPR axi_limit3_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -2996,98 +2896,68 @@ struct clkforce_r { return word; } - clkforce_r copy() volatile - { - return *this; - } - CONSTEXPR uint32_t get_top_level_clk() const - { - uint32_t value = static_cast<uint32_t>(top_level_clk); - return value; - } - uint32_t get_top_level_clk() const volatile - { - uint32_t value = static_cast<uint32_t>(top_level_clk); - return value; - } - CONSTEXPR clkforce_r &set_top_level_clk(uint32_t value) - { - top_level_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); - return *this; - } - CONSTEXPR uint32_t get_cc_clk() const - { - uint32_t value = static_cast<uint32_t>(cc_clk); - return value; - } - uint32_t get_cc_clk() const volatile - { - uint32_t value = static_cast<uint32_t>(cc_clk); - return value; - } - CONSTEXPR clkforce_r &set_cc_clk(uint32_t value) + axi_limit3_r copy() volatile { - cc_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_dma_clk() const + CONSTEXPR uint32_t get_max_beats() const { - uint32_t value = static_cast<uint32_t>(dma_clk); + uint32_t value = static_cast<uint32_t>(max_beats); return value; } - uint32_t get_dma_clk() const volatile + uint32_t get_max_beats() const volatile { - uint32_t value = static_cast<uint32_t>(dma_clk); + uint32_t value = static_cast<uint32_t>(max_beats); return value; } - CONSTEXPR clkforce_r &set_dma_clk(uint32_t value) + CONSTEXPR axi_limit3_r &set_max_beats(uint32_t value) { - dma_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_beats = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_mac_clk() const + CONSTEXPR uint32_t get_memtype() const { - uint32_t value = static_cast<uint32_t>(mac_clk); + uint32_t value = static_cast<uint32_t>(memtype); return value; } - uint32_t get_mac_clk() const volatile + uint32_t get_memtype() const volatile { - uint32_t value = static_cast<uint32_t>(mac_clk); + uint32_t value = static_cast<uint32_t>(memtype); return value; } - CONSTEXPR clkforce_r &set_mac_clk(uint32_t value) + CONSTEXPR axi_limit3_r &set_memtype(uint32_t value) { - mac_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); + memtype = ((1u << 4) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_ao_clk() const + CONSTEXPR uint32_t get_max_outstanding_read_m1() const { - uint32_t value = static_cast<uint32_t>(ao_clk); + uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); return value; } - uint32_t get_ao_clk() const volatile + uint32_t get_max_outstanding_read_m1() const volatile { - uint32_t value = static_cast<uint32_t>(ao_clk); + uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); return value; } - CONSTEXPR clkforce_r &set_ao_clk(uint32_t value) + CONSTEXPR axi_limit3_r &set_max_outstanding_read_m1(uint32_t value) { - ao_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_outstanding_read_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_wd_clk() const + CONSTEXPR uint32_t get_max_outstanding_write_m1() const { - uint32_t value = static_cast<uint32_t>(wd_clk); + uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); return value; } - uint32_t get_wd_clk() const volatile + uint32_t get_max_outstanding_write_m1() const volatile { - uint32_t value = static_cast<uint32_t>(wd_clk); + uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); return value; } - CONSTEXPR clkforce_r &set_wd_clk(uint32_t value) + CONSTEXPR axi_limit3_r &set_max_outstanding_write_m1(uint32_t value) { - wd_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); + max_outstanding_write_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } #endif //__cplusplus @@ -3941,21 +3811,43 @@ struct basep15_r #endif //__cplusplus }; -// pid4_r - Peripheral ID byte 4 (Arm=code 4) -struct pid4_r +// wd_status_r - WD_STATUS of core DEBUGCORE +struct wd_status_r { #ifdef __cplusplus private: #endif //__cplusplus union { - uint32_t PID4; // Byte 4 of Peripheral ID (Lower 8 bits valid) + struct + { + uint32_t core_slice_state : 2; // STATE_HEADER=0, STATE_PALETTE=1, STATE_WEIGHTS=2 + uint32_t core_idle : 1; // Core idle + uint32_t ctrl_state : 2; // IDLE=0, DRAIN=1, OFD_INIT=2, OFD_RUN=3 + uint32_t ctrl_idle : 1; // All stripe jobs idle (all weights consumed) + uint32_t write_buf_index0 : 3; // current write index for next data from core + uint32_t write_buf_valid0 : 1; // write buf valid (full) + uint32_t write_buf_idle0 : 1; // write buf idle (empty) + uint32_t write_buf_index1 : 3; // current write index for next data from core + uint32_t write_buf_valid1 : 1; // write buf valid (full) + uint32_t write_buf_idle1 : 1; // write buf idle (empty) + uint32_t events : 12; // WD events mapped as appendix A + uint32_t reserved0 : 4; + }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR pid4_r() : PID4(static_cast<uint32_t>(0x04)) {} - CONSTEXPR pid4_r(uint32_t init) : word(init) {} + CONSTEXPR wd_status_r() : + core_slice_state(static_cast<uint32_t>(0)), core_idle(static_cast<uint32_t>(0)), + ctrl_state(static_cast<uint32_t>(0)), ctrl_idle(static_cast<uint32_t>(0)), + write_buf_index0(static_cast<uint32_t>(0)), write_buf_valid0(static_cast<uint32_t>(0)), + write_buf_idle0(static_cast<uint32_t>(0)), write_buf_index1(static_cast<uint32_t>(0)), + write_buf_valid1(static_cast<uint32_t>(0)), write_buf_idle1(static_cast<uint32_t>(0)), + events(static_cast<uint32_t>(0)), reserved0(static_cast<uint32_t>(0)) + { + } + CONSTEXPR wd_status_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -3972,202 +3864,224 @@ struct pid4_r { return word; } - pid4_r copy() volatile + wd_status_r copy() volatile { return *this; } - CONSTEXPR uint32_t get_PID4() const + CONSTEXPR uint32_t get_core_slice_state() const { - uint32_t value = static_cast<uint32_t>(PID4); + uint32_t value = static_cast<uint32_t>(core_slice_state); return value; } - uint32_t get_PID4() const volatile + uint32_t get_core_slice_state() const volatile { - uint32_t value = static_cast<uint32_t>(PID4); + uint32_t value = static_cast<uint32_t>(core_slice_state); return value; } - CONSTEXPR pid4_r &set_PID4(uint32_t value) + CONSTEXPR wd_status_r &set_core_slice_state(uint32_t value) { - PID4 = static_cast<uint32_t>(value); + core_slice_state = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// pid5_r - Peripheral ID byte 5 (reserved) -struct pid5_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_core_idle() const { - uint32_t PID5; // Byte 5 of Peripheral ID (Lower 8 bits valid) - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR pid5_r() : PID5(static_cast<uint32_t>(0x00)) {} - CONSTEXPR pid5_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(core_idle); + return value; + } + uint32_t get_core_idle() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(core_idle); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR wd_status_r &set_core_idle(uint32_t value) { - word = value; + core_idle = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_ctrl_state() const { - return word; + uint32_t value = static_cast<uint32_t>(ctrl_state); + return value; } - operator uint32_t() volatile + uint32_t get_ctrl_state() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(ctrl_state); + return value; } - pid5_r copy() volatile + CONSTEXPR wd_status_r &set_ctrl_state(uint32_t value) { + ctrl_state = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_PID5() const + CONSTEXPR uint32_t get_ctrl_idle() const { - uint32_t value = static_cast<uint32_t>(PID5); + uint32_t value = static_cast<uint32_t>(ctrl_idle); return value; } - uint32_t get_PID5() const volatile + uint32_t get_ctrl_idle() const volatile { - uint32_t value = static_cast<uint32_t>(PID5); + uint32_t value = static_cast<uint32_t>(ctrl_idle); return value; } - CONSTEXPR pid5_r &set_PID5(uint32_t value) + CONSTEXPR wd_status_r &set_ctrl_idle(uint32_t value) { - PID5 = static_cast<uint32_t>(value); + ctrl_idle = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// pid6_r - Peripheral ID byte 6 (reserved) -struct pid6_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_write_buf_index0() const { - uint32_t PID6; // Byte 6 of Peripheral ID (Lower 8 bits valid) - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR pid6_r() : PID6(static_cast<uint32_t>(0x00)) {} - CONSTEXPR pid6_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(write_buf_index0); + return value; + } + uint32_t get_write_buf_index0() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(write_buf_index0); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR wd_status_r &set_write_buf_index0(uint32_t value) { - word = value; + write_buf_index0 = ((1u << 3) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_write_buf_valid0() const { - return word; + uint32_t value = static_cast<uint32_t>(write_buf_valid0); + return value; } - operator uint32_t() volatile + uint32_t get_write_buf_valid0() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(write_buf_valid0); + return value; } - pid6_r copy() volatile + CONSTEXPR wd_status_r &set_write_buf_valid0(uint32_t value) { + write_buf_valid0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_PID6() const + CONSTEXPR uint32_t get_write_buf_idle0() const { - uint32_t value = static_cast<uint32_t>(PID6); + uint32_t value = static_cast<uint32_t>(write_buf_idle0); return value; } - uint32_t get_PID6() const volatile + uint32_t get_write_buf_idle0() const volatile { - uint32_t value = static_cast<uint32_t>(PID6); + uint32_t value = static_cast<uint32_t>(write_buf_idle0); return value; } - CONSTEXPR pid6_r &set_PID6(uint32_t value) + CONSTEXPR wd_status_r &set_write_buf_idle0(uint32_t value) { - PID6 = static_cast<uint32_t>(value); + write_buf_idle0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// pid7_r - Peripheral ID byte 7 (reserved) -struct pid7_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_write_buf_index1() const { - uint32_t PID7; // Byte 7 of Peripheral ID (Lower 8 bits valid) - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR pid7_r() : PID7(static_cast<uint32_t>(0x00)) {} - CONSTEXPR pid7_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(write_buf_index1); + return value; + } + uint32_t get_write_buf_index1() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(write_buf_index1); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR wd_status_r &set_write_buf_index1(uint32_t value) { - word = value; + write_buf_index1 = ((1u << 3) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_write_buf_valid1() const { - return word; + uint32_t value = static_cast<uint32_t>(write_buf_valid1); + return value; } - operator uint32_t() volatile + uint32_t get_write_buf_valid1() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(write_buf_valid1); + return value; } - pid7_r copy() volatile + CONSTEXPR wd_status_r &set_write_buf_valid1(uint32_t value) { + write_buf_valid1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_PID7() const + CONSTEXPR uint32_t get_write_buf_idle1() const { - uint32_t value = static_cast<uint32_t>(PID7); + uint32_t value = static_cast<uint32_t>(write_buf_idle1); return value; } - uint32_t get_PID7() const volatile + uint32_t get_write_buf_idle1() const volatile { - uint32_t value = static_cast<uint32_t>(PID7); + uint32_t value = static_cast<uint32_t>(write_buf_idle1); return value; } - CONSTEXPR pid7_r &set_PID7(uint32_t value) + CONSTEXPR wd_status_r &set_write_buf_idle1(uint32_t value) { - PID7 = static_cast<uint32_t>(value); + write_buf_idle1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_events() const + { + uint32_t value = static_cast<uint32_t>(events); + return value; + } + uint32_t get_events() const volatile + { + uint32_t value = static_cast<uint32_t>(events); + return value; + } + CONSTEXPR wd_status_r &set_events(uint32_t value) + { + events = ((1u << 12) - 1) & static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// pid0_r - Peripheral ID byte 0. This is bits[7:0] of the part number. -struct pid0_r +// mac_status_r - MAC_STATUS of core DEBUGCORE +struct mac_status_r { #ifdef __cplusplus private: #endif //__cplusplus union { - uint32_t PID0; // Byte 0 of Peripheral ID (Lower 8 bits valid) + struct + { + uint32_t block_cfg_valid : 1; // MAC has a valid block configuration + uint32_t trav_en : 1; // MAC is doing block traversal + uint32_t wait_for_ib : 1; // MAC is waiting for an Input Buffer to become available + uint32_t wait_for_acc_buf : 1; // MAC is waiting for an Accumulator Buffer to become available + uint32_t wait_for_weights : 1; // MAC is waiting for a Weight Block to become available + uint32_t stall_stripe : 1; // MAC is stalling between two stripes + uint32_t dw_sel : 1; // Currently used weight interface in MAC AI + uint32_t wait_for_dw0_ready : 1; // MAC AI is waiting for MAC DPU to send dw0_ready to WD + uint32_t wait_for_dw1_ready : 1; // MAC AI is waiting for MAC DPU to send dw1_ready to WD + uint32_t acc_buf_sel_ai : 1; // Currently used AccBuf interface in MAC AI + uint32_t wait_for_acc0_ready : 1; // MAC AI is waiting for acc0_ready from AO + uint32_t wait_for_acc1_ready : 1; // MAC AI is waiting for acc1_ready from AO + uint32_t acc_buf_sel_aa : 1; // Currently used AccBuf interface in MAC ADDER_ARRAY + uint32_t acc0_valid : 1; // MAC outgoing value of acc0_valid + uint32_t acc1_valid : 1; // MAC outgoing value of acc1_valid + uint32_t reserved0 : 1; + uint32_t events : 11; // Mapped to MAC events described in Appendix A + uint32_t reserved1 : 5; + }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR pid0_r() : PID0(static_cast<uint32_t>(0x80)) {} - CONSTEXPR pid0_r(uint32_t init) : word(init) {} + CONSTEXPR mac_status_r() : + block_cfg_valid(static_cast<uint32_t>(0)), trav_en(static_cast<uint32_t>(0)), + wait_for_ib(static_cast<uint32_t>(0)), wait_for_acc_buf(static_cast<uint32_t>(0)), + wait_for_weights(static_cast<uint32_t>(0)), stall_stripe(static_cast<uint32_t>(0)), + dw_sel(static_cast<uint32_t>(0)), wait_for_dw0_ready(static_cast<uint32_t>(0)), + wait_for_dw1_ready(static_cast<uint32_t>(0)), acc_buf_sel_ai(static_cast<uint32_t>(0)), + wait_for_acc0_ready(static_cast<uint32_t>(0)), wait_for_acc1_ready(static_cast<uint32_t>(0)), + acc_buf_sel_aa(static_cast<uint32_t>(0)), acc0_valid(static_cast<uint32_t>(0)), + acc1_valid(static_cast<uint32_t>(0)), reserved0(static_cast<uint32_t>(0)), events(static_cast<uint32_t>(0)), + reserved1(static_cast<uint32_t>(0)) + { + } + CONSTEXPR mac_status_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -4184,309 +4098,288 @@ struct pid0_r { return word; } - pid0_r copy() volatile + mac_status_r copy() volatile { return *this; } - CONSTEXPR uint32_t get_PID0() const + CONSTEXPR uint32_t get_block_cfg_valid() const { - uint32_t value = static_cast<uint32_t>(PID0); + uint32_t value = static_cast<uint32_t>(block_cfg_valid); return value; } - uint32_t get_PID0() const volatile + uint32_t get_block_cfg_valid() const volatile { - uint32_t value = static_cast<uint32_t>(PID0); + uint32_t value = static_cast<uint32_t>(block_cfg_valid); return value; } - CONSTEXPR pid0_r &set_PID0(uint32_t value) + CONSTEXPR mac_status_r &set_block_cfg_valid(uint32_t value) { - PID0 = static_cast<uint32_t>(value); + block_cfg_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// pid1_r - Peripheral ID byte 1. This is bits[11:8] of the part number in bits[3:0], and bits[3:0] of the Arm ID in -// bits[7:4]. -struct pid1_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_trav_en() const { - uint32_t PID1; // Byte 1 of Peripheral ID (Lower 8 bits valid) - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR pid1_r() : PID1(static_cast<uint32_t>(0xB5)) {} - CONSTEXPR pid1_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(trav_en); + return value; + } + uint32_t get_trav_en() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(trav_en); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR mac_status_r &set_trav_en(uint32_t value) { - word = value; + trav_en = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_wait_for_ib() const { - return word; + uint32_t value = static_cast<uint32_t>(wait_for_ib); + return value; } - operator uint32_t() volatile + uint32_t get_wait_for_ib() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(wait_for_ib); + return value; } - pid1_r copy() volatile + CONSTEXPR mac_status_r &set_wait_for_ib(uint32_t value) { + wait_for_ib = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_PID1() const + CONSTEXPR uint32_t get_wait_for_acc_buf() const { - uint32_t value = static_cast<uint32_t>(PID1); + uint32_t value = static_cast<uint32_t>(wait_for_acc_buf); return value; } - uint32_t get_PID1() const volatile + uint32_t get_wait_for_acc_buf() const volatile { - uint32_t value = static_cast<uint32_t>(PID1); + uint32_t value = static_cast<uint32_t>(wait_for_acc_buf); return value; } - CONSTEXPR pid1_r &set_PID1(uint32_t value) + CONSTEXPR mac_status_r &set_wait_for_acc_buf(uint32_t value) { - PID1 = static_cast<uint32_t>(value); + wait_for_acc_buf = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// pid2_r - Peripheral ID byte 2. This is bits[6:4] of the Arm ID in bits[2:0], and bit 3 indicates format B. -struct pid2_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_wait_for_weights() const { - uint32_t PID2; // Byte 2 of Peripheral ID (Lower 8 bits valid) - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR pid2_r() : PID2(static_cast<uint32_t>(0x0B)) {} - CONSTEXPR pid2_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(wait_for_weights); + return value; + } + uint32_t get_wait_for_weights() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(wait_for_weights); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR mac_status_r &set_wait_for_weights(uint32_t value) { - word = value; + wait_for_weights = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_stall_stripe() const { - return word; + uint32_t value = static_cast<uint32_t>(stall_stripe); + return value; } - operator uint32_t() volatile + uint32_t get_stall_stripe() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(stall_stripe); + return value; } - pid2_r copy() volatile + CONSTEXPR mac_status_r &set_stall_stripe(uint32_t value) { + stall_stripe = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_PID2() const + CONSTEXPR uint32_t get_dw_sel() const { - uint32_t value = static_cast<uint32_t>(PID2); + uint32_t value = static_cast<uint32_t>(dw_sel); return value; } - uint32_t get_PID2() const volatile + uint32_t get_dw_sel() const volatile { - uint32_t value = static_cast<uint32_t>(PID2); + uint32_t value = static_cast<uint32_t>(dw_sel); return value; } - CONSTEXPR pid2_r &set_PID2(uint32_t value) + CONSTEXPR mac_status_r &set_dw_sel(uint32_t value) { - PID2 = static_cast<uint32_t>(value); + dw_sel = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// pid3_r - Peripheral ID byte 3. -struct pid3_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_wait_for_dw0_ready() const { - uint32_t PID3; // Byte 1 of Peripheral ID (Lower 8 bits valid) - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR pid3_r() : PID3(static_cast<uint32_t>(0x0)) {} - CONSTEXPR pid3_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(wait_for_dw0_ready); + return value; + } + uint32_t get_wait_for_dw0_ready() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(wait_for_dw0_ready); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR mac_status_r &set_wait_for_dw0_ready(uint32_t value) { - word = value; + wait_for_dw0_ready = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_wait_for_dw1_ready() const { - return word; + uint32_t value = static_cast<uint32_t>(wait_for_dw1_ready); + return value; } - operator uint32_t() volatile + uint32_t get_wait_for_dw1_ready() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(wait_for_dw1_ready); + return value; } - pid3_r copy() volatile + CONSTEXPR mac_status_r &set_wait_for_dw1_ready(uint32_t value) { + wait_for_dw1_ready = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_PID3() const + CONSTEXPR uint32_t get_acc_buf_sel_ai() const { - uint32_t value = static_cast<uint32_t>(PID3); + uint32_t value = static_cast<uint32_t>(acc_buf_sel_ai); return value; } - uint32_t get_PID3() const volatile + uint32_t get_acc_buf_sel_ai() const volatile { - uint32_t value = static_cast<uint32_t>(PID3); + uint32_t value = static_cast<uint32_t>(acc_buf_sel_ai); return value; } - CONSTEXPR pid3_r &set_PID3(uint32_t value) + CONSTEXPR mac_status_r &set_acc_buf_sel_ai(uint32_t value) { - PID3 = static_cast<uint32_t>(value); + acc_buf_sel_ai = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// cid0_r - Component ID byte 0. -struct cid0_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_wait_for_acc0_ready() const { - uint32_t CID0; // Byte 0 of Component ID (Lower 8 bits valid) - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR cid0_r() : CID0(static_cast<uint32_t>(0x0D)) {} - CONSTEXPR cid0_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(wait_for_acc0_ready); + return value; + } + uint32_t get_wait_for_acc0_ready() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(wait_for_acc0_ready); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR mac_status_r &set_wait_for_acc0_ready(uint32_t value) { - word = value; + wait_for_acc0_ready = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_wait_for_acc1_ready() const { - return word; + uint32_t value = static_cast<uint32_t>(wait_for_acc1_ready); + return value; } - operator uint32_t() volatile + uint32_t get_wait_for_acc1_ready() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(wait_for_acc1_ready); + return value; } - cid0_r copy() volatile + CONSTEXPR mac_status_r &set_wait_for_acc1_ready(uint32_t value) { + wait_for_acc1_ready = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_CID0() const + CONSTEXPR uint32_t get_acc_buf_sel_aa() const { - uint32_t value = static_cast<uint32_t>(CID0); + uint32_t value = static_cast<uint32_t>(acc_buf_sel_aa); return value; } - uint32_t get_CID0() const volatile + uint32_t get_acc_buf_sel_aa() const volatile { - uint32_t value = static_cast<uint32_t>(CID0); + uint32_t value = static_cast<uint32_t>(acc_buf_sel_aa); return value; } - CONSTEXPR cid0_r &set_CID0(uint32_t value) + CONSTEXPR mac_status_r &set_acc_buf_sel_aa(uint32_t value) { - CID0 = static_cast<uint32_t>(value); + acc_buf_sel_aa = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// cid1_r - Component ID byte 1. -struct cid1_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_acc0_valid() const { - uint32_t CID1; // Byte 1 of Component ID (Lower 8 bits valid) - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR cid1_r() : CID1(static_cast<uint32_t>(0xF0)) {} - CONSTEXPR cid1_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(acc0_valid); + return value; + } + uint32_t get_acc0_valid() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(acc0_valid); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR mac_status_r &set_acc0_valid(uint32_t value) { - word = value; + acc0_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_acc1_valid() const { - return word; + uint32_t value = static_cast<uint32_t>(acc1_valid); + return value; } - operator uint32_t() volatile + uint32_t get_acc1_valid() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(acc1_valid); + return value; } - cid1_r copy() volatile + CONSTEXPR mac_status_r &set_acc1_valid(uint32_t value) { + acc1_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_CID1() const + CONSTEXPR uint32_t get_events() const { - uint32_t value = static_cast<uint32_t>(CID1); + uint32_t value = static_cast<uint32_t>(events); return value; } - uint32_t get_CID1() const volatile + uint32_t get_events() const volatile { - uint32_t value = static_cast<uint32_t>(CID1); + uint32_t value = static_cast<uint32_t>(events); return value; } - CONSTEXPR cid1_r &set_CID1(uint32_t value) + CONSTEXPR mac_status_r &set_events(uint32_t value) { - CID1 = static_cast<uint32_t>(value); + events = ((1u << 11) - 1) & static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// cid2_r - Component ID byte 2. -struct cid2_r +// ao_status_r - AO_STATUS of core DEBUGCORE +struct ao_status_r { #ifdef __cplusplus private: #endif //__cplusplus union { - uint32_t CID2; // Byte 2 of Component ID (Lower 8 bits valid) + struct + { + uint32_t cmd_sbw_valid : 1; // Block command to shared buffer write module is valid. + uint32_t cmd_act_valid : 1; // Block command to activation function module is valid. + uint32_t cmd_ctl_valid : 1; // Block command to control module is valid. + uint32_t cmd_scl_valid : 1; // Block command to scale module is valid. + uint32_t cmd_sbr_valid : 1; // Block command to shared buffer read module is valid. + uint32_t cmd_ofm_valid : 1; // Block command to ofm parameter module is valid. + uint32_t blk_cmd_ready : 1; // Ready to accept block command. + uint32_t blk_cmd_valid : 1; // Block command from CC is valid. + uint32_t reserved0 : 8; + uint32_t events : 8; // Mapped to AO events described in Appendix A. + uint32_t reserved1 : 8; + }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR cid2_r() : CID2(static_cast<uint32_t>(0x05)) {} - CONSTEXPR cid2_r(uint32_t init) : word(init) {} + CONSTEXPR ao_status_r() : + cmd_sbw_valid(static_cast<uint32_t>(0)), cmd_act_valid(static_cast<uint32_t>(0)), + cmd_ctl_valid(static_cast<uint32_t>(0)), cmd_scl_valid(static_cast<uint32_t>(0)), + cmd_sbr_valid(static_cast<uint32_t>(0)), cmd_ofm_valid(static_cast<uint32_t>(0)), + blk_cmd_ready(static_cast<uint32_t>(0)), blk_cmd_valid(static_cast<uint32_t>(0)), + reserved0(static_cast<uint32_t>(0)), events(static_cast<uint32_t>(0)), reserved1(static_cast<uint32_t>(0)) + { + } + CONSTEXPR ao_status_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -4503,83 +4396,150 @@ struct cid2_r { return word; } - cid2_r copy() volatile + ao_status_r copy() volatile { return *this; } - CONSTEXPR uint32_t get_CID2() const + CONSTEXPR uint32_t get_cmd_sbw_valid() const { - uint32_t value = static_cast<uint32_t>(CID2); + uint32_t value = static_cast<uint32_t>(cmd_sbw_valid); return value; } - uint32_t get_CID2() const volatile + uint32_t get_cmd_sbw_valid() const volatile { - uint32_t value = static_cast<uint32_t>(CID2); + uint32_t value = static_cast<uint32_t>(cmd_sbw_valid); return value; } - CONSTEXPR cid2_r &set_CID2(uint32_t value) + CONSTEXPR ao_status_r &set_cmd_sbw_valid(uint32_t value) { - CID2 = static_cast<uint32_t>(value); + cmd_sbw_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// cid3_r - Component ID byte 3. -struct cid3_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_cmd_act_valid() const { - uint32_t CID3; // Byte 3 of Component ID (Lower 8 bits valid) - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR cid3_r() : CID3(static_cast<uint32_t>(0xB1)) {} - CONSTEXPR cid3_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(cmd_act_valid); + return value; + } + uint32_t get_cmd_act_valid() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(cmd_act_valid); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR ao_status_r &set_cmd_act_valid(uint32_t value) { - word = value; + cmd_act_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_cmd_ctl_valid() const { - return word; + uint32_t value = static_cast<uint32_t>(cmd_ctl_valid); + return value; } - operator uint32_t() volatile + uint32_t get_cmd_ctl_valid() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(cmd_ctl_valid); + return value; } - cid3_r copy() volatile + CONSTEXPR ao_status_r &set_cmd_ctl_valid(uint32_t value) { + cmd_ctl_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_CID3() const + CONSTEXPR uint32_t get_cmd_scl_valid() const { - uint32_t value = static_cast<uint32_t>(CID3); + uint32_t value = static_cast<uint32_t>(cmd_scl_valid); return value; } - uint32_t get_CID3() const volatile + uint32_t get_cmd_scl_valid() const volatile { - uint32_t value = static_cast<uint32_t>(CID3); + uint32_t value = static_cast<uint32_t>(cmd_scl_valid); return value; } - CONSTEXPR cid3_r &set_CID3(uint32_t value) + CONSTEXPR ao_status_r &set_cmd_scl_valid(uint32_t value) { - CID3 = static_cast<uint32_t>(value); + cmd_scl_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_cmd_sbr_valid() const + { + uint32_t value = static_cast<uint32_t>(cmd_sbr_valid); + return value; + } + uint32_t get_cmd_sbr_valid() const volatile + { + uint32_t value = static_cast<uint32_t>(cmd_sbr_valid); + return value; + } + CONSTEXPR ao_status_r &set_cmd_sbr_valid(uint32_t value) + { + cmd_sbr_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_cmd_ofm_valid() const + { + uint32_t value = static_cast<uint32_t>(cmd_ofm_valid); + return value; + } + uint32_t get_cmd_ofm_valid() const volatile + { + uint32_t value = static_cast<uint32_t>(cmd_ofm_valid); + return value; + } + CONSTEXPR ao_status_r &set_cmd_ofm_valid(uint32_t value) + { + cmd_ofm_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_blk_cmd_ready() const + { + uint32_t value = static_cast<uint32_t>(blk_cmd_ready); + return value; + } + uint32_t get_blk_cmd_ready() const volatile + { + uint32_t value = static_cast<uint32_t>(blk_cmd_ready); + return value; + } + CONSTEXPR ao_status_r &set_blk_cmd_ready(uint32_t value) + { + blk_cmd_ready = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_blk_cmd_valid() const + { + uint32_t value = static_cast<uint32_t>(blk_cmd_valid); + return value; + } + uint32_t get_blk_cmd_valid() const volatile + { + uint32_t value = static_cast<uint32_t>(blk_cmd_valid); + return value; + } + CONSTEXPR ao_status_r &set_blk_cmd_valid(uint32_t value) + { + blk_cmd_valid = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_events() const + { + uint32_t value = static_cast<uint32_t>(events); + return value; + } + uint32_t get_events() const volatile + { + uint32_t value = static_cast<uint32_t>(events); + return value; + } + CONSTEXPR ao_status_r &set_events(uint32_t value) + { + events = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// id_r - ID register -struct id_r +// dma_status0_r - DMA_STATUS0 of core DEBUGCORE +struct dma_status0_r { #ifdef __cplusplus private: @@ -4588,28 +4548,65 @@ struct id_r { struct { - uint32_t version_status : 4; // This is the version of the product - uint32_t version_minor : 4; // This is the n for the P part of an RnPn release number - uint32_t version_major : 4; // This is the n for the R part of an RnPn release number - uint32_t product_major : 4; // This is the X part of the ML00X product number - uint32_t arch_patch_rev : 4; // This is the patch number of the architecture version a.b - uint32_t - arch_minor_rev : 8; // This is the minor architecture version number, b in the architecture version a.b - uint32_t - arch_major_rev : 4; // This is the major architecture version number, a in the architecture version a.b + uint32_t CMD_IDLE : 1; // When this bit is high means that the CMD block is not busy in generating addresses + // for a CMD job. + uint32_t IFM_IDLE : 1; // When this bit is high means that there are no ongoing IFM jobs + uint32_t WGT_IDLE_C0 : 1; // When this bit is high means that the WGT block is not busy in generating + // addresses for a WGT job + uint32_t BAS_IDLE_C0 : 1; // When this bit is high means that the BAS block is not busy in generating + // addresses for a BAS job + uint32_t M2M_IDLE : 1; // When this bit is high means that there are no ongoing M2M jobs + uint32_t OFM_IDLE : 1; // When this bit is high means that there are no ongoing OFM jobs + uint32_t HALT_REQ : 1; // CPM has requested to HALT AXI bus before soft reset + uint32_t HALT_ACK : 1; // DMA is in condition to halt the AXI bus since there are no pending transactions + uint32_t PAUSE_REQ : 1; // CC has requested to pause the AXI + uint32_t PAUSE_ACK : 1; // DMA is in condition to pause the AXI bus since there are no pending transactions + uint32_t IB0_AI_VALID_C0 : 1; // Data for AI to be read in IFM input buffer 0 - Core 0 + uint32_t IB0_AI_READY_C0 : 1; // Data consumed from AI in IFM input buffer 0 - Core 0 + uint32_t IB1_AI_VALID_C0 : 1; // Data for AI to be read in IFM input buffer 1 - Core 0 + uint32_t IB1_AI_READY_C0 : 1; // Data consumed from AI in IFM input buffer 1 - Core 0 + uint32_t IB0_AO_VALID_C0 : 1; // Data for AO to be read in IFM input buffer 0 - Core 0 + uint32_t IB0_AO_READY_C0 : 1; // Data consumed from AO in IFM input buffer 0 - Core 0 + uint32_t IB1_AO_VALID_C0 : 1; // Data for AO to be read in IFM input buffer 0 - Core 0 + uint32_t IB1_AO_READY_C0 : 1; // Data consumed from AO in IFM input buffer 1 - Core 0 + uint32_t OB0_VALID_C0 : 1; // Data for DMA ready to be consumed in OFM output buffer 0 - Core 0 + uint32_t OB0_READY_C0 : 1; // Data consumed from DMA in OFM output buffer 0 - Core 0 + uint32_t OB1_VALID_C0 : 1; // Data for DMA ready to be consumed in OFM output buffer 1 - Core 0 + uint32_t OB1_READY_C0 : 1; // Data consumed from DMA in OFM output buffer 1 - Core 0 + uint32_t CMD_VALID : 1; // New command word for CC to be consumed + uint32_t CMD_READY : 1; // command word consumed by CC + uint32_t WD_BITSTREAM_VALID_C0 : 1; // New weight word for WD to be consumed - Core 0 + uint32_t WD_BITSTREAM_READY_C0 : 1; // Weight word consumed by WD - Core 0 + uint32_t BS_BITSTREAM_VALID_C0 : 1; // New BaS word for AO to be consumed - Core 0 + uint32_t BS_BITSTREAM_READY_C0 : 1; // BaS word consumed by AO - Core 0 + uint32_t AXI0_AR_STALLED : 1; // Read transfer request stalled on arready low AXI0 (due to memory system) + uint32_t AXI0_RD_LIMIT_STALL : 1; // Read stalled due to one AXI0 limit counter being reached + uint32_t AXI0_AW_STALLED : 1; // Write transfer request stalled on awready low AXI0 (due to memory system) + uint32_t AXI0_W_STALLED : 1; // Write transfer stalled on awready low AXI0 (due to memory system) }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR id_r() : - version_status(static_cast<uint32_t>(1)), version_minor(static_cast<uint32_t>(0x0)), - version_major(static_cast<uint32_t>(0x0)), product_major(static_cast<uint32_t>(4)), - arch_patch_rev(static_cast<uint32_t>(0)), arch_minor_rev(static_cast<uint32_t>(0)), - arch_major_rev(static_cast<uint32_t>(1)) + CONSTEXPR dma_status0_r() : + CMD_IDLE(static_cast<uint32_t>(0)), IFM_IDLE(static_cast<uint32_t>(0)), WGT_IDLE_C0(static_cast<uint32_t>(0)), + BAS_IDLE_C0(static_cast<uint32_t>(0)), M2M_IDLE(static_cast<uint32_t>(0)), OFM_IDLE(static_cast<uint32_t>(0)), + HALT_REQ(static_cast<uint32_t>(0)), HALT_ACK(static_cast<uint32_t>(0)), PAUSE_REQ(static_cast<uint32_t>(0)), + PAUSE_ACK(static_cast<uint32_t>(0)), IB0_AI_VALID_C0(static_cast<uint32_t>(0)), + IB0_AI_READY_C0(static_cast<uint32_t>(0)), IB1_AI_VALID_C0(static_cast<uint32_t>(0)), + IB1_AI_READY_C0(static_cast<uint32_t>(0)), IB0_AO_VALID_C0(static_cast<uint32_t>(0)), + IB0_AO_READY_C0(static_cast<uint32_t>(0)), IB1_AO_VALID_C0(static_cast<uint32_t>(0)), + IB1_AO_READY_C0(static_cast<uint32_t>(0)), OB0_VALID_C0(static_cast<uint32_t>(0)), + OB0_READY_C0(static_cast<uint32_t>(0)), OB1_VALID_C0(static_cast<uint32_t>(0)), + OB1_READY_C0(static_cast<uint32_t>(0)), CMD_VALID(static_cast<uint32_t>(0)), + CMD_READY(static_cast<uint32_t>(0)), WD_BITSTREAM_VALID_C0(static_cast<uint32_t>(0)), + WD_BITSTREAM_READY_C0(static_cast<uint32_t>(0)), BS_BITSTREAM_VALID_C0(static_cast<uint32_t>(0)), + BS_BITSTREAM_READY_C0(static_cast<uint32_t>(0)), AXI0_AR_STALLED(static_cast<uint32_t>(0)), + AXI0_RD_LIMIT_STALL(static_cast<uint32_t>(0)), AXI0_AW_STALLED(static_cast<uint32_t>(0)), + AXI0_W_STALLED(static_cast<uint32_t>(0)) { } - CONSTEXPR id_r(uint32_t init) : word(init) {} + CONSTEXPR dma_status0_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -4626,500 +4623,495 @@ struct id_r { return word; } - id_r copy() volatile + dma_status0_r copy() volatile { return *this; } - CONSTEXPR uint32_t get_version_status() const + CONSTEXPR uint32_t get_CMD_IDLE() const { - uint32_t value = static_cast<uint32_t>(version_status); + uint32_t value = static_cast<uint32_t>(CMD_IDLE); return value; } - uint32_t get_version_status() const volatile + uint32_t get_CMD_IDLE() const volatile { - uint32_t value = static_cast<uint32_t>(version_status); + uint32_t value = static_cast<uint32_t>(CMD_IDLE); return value; } - CONSTEXPR id_r &set_version_status(uint32_t value) + CONSTEXPR dma_status0_r &set_CMD_IDLE(uint32_t value) { - version_status = ((1u << 4) - 1) & static_cast<uint32_t>(value); + CMD_IDLE = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_version_minor() const + CONSTEXPR uint32_t get_IFM_IDLE() const { - uint32_t value = static_cast<uint32_t>(version_minor); + uint32_t value = static_cast<uint32_t>(IFM_IDLE); return value; } - uint32_t get_version_minor() const volatile + uint32_t get_IFM_IDLE() const volatile { - uint32_t value = static_cast<uint32_t>(version_minor); + uint32_t value = static_cast<uint32_t>(IFM_IDLE); return value; } - CONSTEXPR id_r &set_version_minor(uint32_t value) + CONSTEXPR dma_status0_r &set_IFM_IDLE(uint32_t value) { - version_minor = ((1u << 4) - 1) & static_cast<uint32_t>(value); + IFM_IDLE = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_version_major() const + CONSTEXPR uint32_t get_WGT_IDLE_C0() const { - uint32_t value = static_cast<uint32_t>(version_major); + uint32_t value = static_cast<uint32_t>(WGT_IDLE_C0); return value; } - uint32_t get_version_major() const volatile + uint32_t get_WGT_IDLE_C0() const volatile { - uint32_t value = static_cast<uint32_t>(version_major); + uint32_t value = static_cast<uint32_t>(WGT_IDLE_C0); return value; } - CONSTEXPR id_r &set_version_major(uint32_t value) + CONSTEXPR dma_status0_r &set_WGT_IDLE_C0(uint32_t value) { - version_major = ((1u << 4) - 1) & static_cast<uint32_t>(value); + WGT_IDLE_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_product_major() const + CONSTEXPR uint32_t get_BAS_IDLE_C0() const { - uint32_t value = static_cast<uint32_t>(product_major); + uint32_t value = static_cast<uint32_t>(BAS_IDLE_C0); return value; } - uint32_t get_product_major() const volatile + uint32_t get_BAS_IDLE_C0() const volatile { - uint32_t value = static_cast<uint32_t>(product_major); + uint32_t value = static_cast<uint32_t>(BAS_IDLE_C0); return value; } - CONSTEXPR id_r &set_product_major(uint32_t value) + CONSTEXPR dma_status0_r &set_BAS_IDLE_C0(uint32_t value) { - product_major = ((1u << 4) - 1) & static_cast<uint32_t>(value); + BAS_IDLE_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_arch_patch_rev() const + CONSTEXPR uint32_t get_M2M_IDLE() const { - uint32_t value = static_cast<uint32_t>(arch_patch_rev); + uint32_t value = static_cast<uint32_t>(M2M_IDLE); return value; } - uint32_t get_arch_patch_rev() const volatile + uint32_t get_M2M_IDLE() const volatile { - uint32_t value = static_cast<uint32_t>(arch_patch_rev); + uint32_t value = static_cast<uint32_t>(M2M_IDLE); return value; } - CONSTEXPR id_r &set_arch_patch_rev(uint32_t value) + CONSTEXPR dma_status0_r &set_M2M_IDLE(uint32_t value) { - arch_patch_rev = ((1u << 4) - 1) & static_cast<uint32_t>(value); + M2M_IDLE = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_arch_minor_rev() const + CONSTEXPR uint32_t get_OFM_IDLE() const { - uint32_t value = static_cast<uint32_t>(arch_minor_rev); + uint32_t value = static_cast<uint32_t>(OFM_IDLE); return value; } - uint32_t get_arch_minor_rev() const volatile + uint32_t get_OFM_IDLE() const volatile { - uint32_t value = static_cast<uint32_t>(arch_minor_rev); + uint32_t value = static_cast<uint32_t>(OFM_IDLE); return value; } - CONSTEXPR id_r &set_arch_minor_rev(uint32_t value) + CONSTEXPR dma_status0_r &set_OFM_IDLE(uint32_t value) { - arch_minor_rev = ((1u << 8) - 1) & static_cast<uint32_t>(value); + OFM_IDLE = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_arch_major_rev() const + CONSTEXPR uint32_t get_HALT_REQ() const { - uint32_t value = static_cast<uint32_t>(arch_major_rev); + uint32_t value = static_cast<uint32_t>(HALT_REQ); return value; } - uint32_t get_arch_major_rev() const volatile + uint32_t get_HALT_REQ() const volatile { - uint32_t value = static_cast<uint32_t>(arch_major_rev); + uint32_t value = static_cast<uint32_t>(HALT_REQ); return value; } - CONSTEXPR id_r &set_arch_major_rev(uint32_t value) + CONSTEXPR dma_status0_r &set_HALT_REQ(uint32_t value) { - arch_major_rev = ((1u << 4) - 1) & static_cast<uint32_t>(value); + HALT_REQ = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// status_r - Register describes the current operating status of the NPU -struct status_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_HALT_ACK() const { - struct - { - uint32_t state : 1; // NPU state, 0 = Stopped, 1 = Running - uint32_t irq_raised : 1; // Raw IRQ status, 0 = IRQ not raised, 1 = IRQ raised. IRQ is cleared using command - // register bit 1 - uint32_t - bus_status : 1; // 0=OK, 1=Bus abort detected and processing halted (NPU will reach IDLE state and not - // to start process any more commands/AXI transactions). Can only be cleared by a reset - uint32_t reset_status : 1; // Reset is ongoing and only this register can be read (other registers read as 0 - // and writes are ignored.) A value of 0 means NPU is not being reset and can be - // accessed as normal - uint32_t - cmd_parse_error : 1; // 0=No error 1=Command stream parsing error detected. Can only be cleared by reset - uint32_t cmd_end_reached : 1; // 0=Not reached, 1=Reached. Cleared by writing QBASE or QSIZE when NPU is in - // stopped state - uint32_t pmu_irq_raised : 1; // 0=No PMU IRQ, 1=PMU IRQ raised. Cleared by using command register bit 1 - uint32_t wd_fault : 1; // Weight decoder state: 0=no fault 1=weight decoder decompression fault. Can only be - // cleared by reset - uint32_t reserved0 : 3; - uint32_t faulting_interface : 1; // Faulting interface on bus abort. 0=AXI-M0 1=AXI-M1 - uint32_t faulting_channel : 4; // Faulting channel on a bus abort. Read: 0=Cmd 1=IFM 2=Weights 3=Scale+Bias - // 4=Mem2Mem; Write: 8=OFM 9=Mem2Mem - uint32_t irq_history_mask : 16; // IRQ History mask - }; - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR status_r() : - state(static_cast<uint32_t>(::state::STOPPED)), irq_raised(static_cast<uint32_t>(0x0)), - bus_status(static_cast<uint32_t>(0x0)), reset_status(static_cast<uint32_t>(0x1)), - cmd_parse_error(static_cast<uint32_t>(0x0)), cmd_end_reached(static_cast<uint32_t>(0x0)), - pmu_irq_raised(static_cast<uint32_t>(0x0)), wd_fault(static_cast<uint32_t>(0x0)), - reserved0(static_cast<uint32_t>(0)), faulting_interface(static_cast<uint32_t>(0x0)), - faulting_channel(static_cast<uint32_t>(0x0)), irq_history_mask(static_cast<uint32_t>(0x0)) + uint32_t value = static_cast<uint32_t>(HALT_ACK); + return value; + } + uint32_t get_HALT_ACK() const volatile { + uint32_t value = static_cast<uint32_t>(HALT_ACK); + return value; } - CONSTEXPR status_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + CONSTEXPR dma_status0_r &set_HALT_ACK(uint32_t value) { - word = value; + HALT_ACK = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - void operator=(uint32_t value) volatile + CONSTEXPR uint32_t get_PAUSE_REQ() const { - word = value; + uint32_t value = static_cast<uint32_t>(PAUSE_REQ); + return value; } - CONSTEXPR operator uint32_t() + uint32_t get_PAUSE_REQ() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(PAUSE_REQ); + return value; } - operator uint32_t() volatile + CONSTEXPR dma_status0_r &set_PAUSE_REQ(uint32_t value) { - return word; + PAUSE_REQ = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - status_r copy() volatile + CONSTEXPR uint32_t get_PAUSE_ACK() const { + uint32_t value = static_cast<uint32_t>(PAUSE_ACK); + return value; + } + uint32_t get_PAUSE_ACK() const volatile + { + uint32_t value = static_cast<uint32_t>(PAUSE_ACK); + return value; + } + CONSTEXPR dma_status0_r &set_PAUSE_ACK(uint32_t value) + { + PAUSE_ACK = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR ::state get_state() const + CONSTEXPR uint32_t get_IB0_AI_VALID_C0() const { - ::state value = static_cast<::state>(state); + uint32_t value = static_cast<uint32_t>(IB0_AI_VALID_C0); return value; } - ::state get_state() const volatile + uint32_t get_IB0_AI_VALID_C0() const volatile { - ::state value = static_cast<::state>(state); + uint32_t value = static_cast<uint32_t>(IB0_AI_VALID_C0); return value; } - CONSTEXPR status_r &set_state(::state value) + CONSTEXPR dma_status0_r &set_IB0_AI_VALID_C0(uint32_t value) { - state = ((1u << 1) - 1) & static_cast<uint32_t>(value); + IB0_AI_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_irq_raised() const + CONSTEXPR uint32_t get_IB0_AI_READY_C0() const { - uint32_t value = static_cast<uint32_t>(irq_raised); + uint32_t value = static_cast<uint32_t>(IB0_AI_READY_C0); return value; } - uint32_t get_irq_raised() const volatile + uint32_t get_IB0_AI_READY_C0() const volatile { - uint32_t value = static_cast<uint32_t>(irq_raised); + uint32_t value = static_cast<uint32_t>(IB0_AI_READY_C0); return value; } - CONSTEXPR status_r &set_irq_raised(uint32_t value) + CONSTEXPR dma_status0_r &set_IB0_AI_READY_C0(uint32_t value) { - irq_raised = ((1u << 1) - 1) & static_cast<uint32_t>(value); + IB0_AI_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_bus_status() const + CONSTEXPR uint32_t get_IB1_AI_VALID_C0() const { - uint32_t value = static_cast<uint32_t>(bus_status); + uint32_t value = static_cast<uint32_t>(IB1_AI_VALID_C0); return value; } - uint32_t get_bus_status() const volatile + uint32_t get_IB1_AI_VALID_C0() const volatile { - uint32_t value = static_cast<uint32_t>(bus_status); + uint32_t value = static_cast<uint32_t>(IB1_AI_VALID_C0); return value; } - CONSTEXPR status_r &set_bus_status(uint32_t value) + CONSTEXPR dma_status0_r &set_IB1_AI_VALID_C0(uint32_t value) { - bus_status = ((1u << 1) - 1) & static_cast<uint32_t>(value); + IB1_AI_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_reset_status() const + CONSTEXPR uint32_t get_IB1_AI_READY_C0() const { - uint32_t value = static_cast<uint32_t>(reset_status); + uint32_t value = static_cast<uint32_t>(IB1_AI_READY_C0); return value; } - uint32_t get_reset_status() const volatile + uint32_t get_IB1_AI_READY_C0() const volatile { - uint32_t value = static_cast<uint32_t>(reset_status); + uint32_t value = static_cast<uint32_t>(IB1_AI_READY_C0); return value; } - CONSTEXPR status_r &set_reset_status(uint32_t value) + CONSTEXPR dma_status0_r &set_IB1_AI_READY_C0(uint32_t value) { - reset_status = ((1u << 1) - 1) & static_cast<uint32_t>(value); + IB1_AI_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_cmd_parse_error() const + CONSTEXPR uint32_t get_IB0_AO_VALID_C0() const { - uint32_t value = static_cast<uint32_t>(cmd_parse_error); + uint32_t value = static_cast<uint32_t>(IB0_AO_VALID_C0); return value; } - uint32_t get_cmd_parse_error() const volatile + uint32_t get_IB0_AO_VALID_C0() const volatile { - uint32_t value = static_cast<uint32_t>(cmd_parse_error); + uint32_t value = static_cast<uint32_t>(IB0_AO_VALID_C0); return value; } - CONSTEXPR status_r &set_cmd_parse_error(uint32_t value) + CONSTEXPR dma_status0_r &set_IB0_AO_VALID_C0(uint32_t value) { - cmd_parse_error = ((1u << 1) - 1) & static_cast<uint32_t>(value); + IB0_AO_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_cmd_end_reached() const + CONSTEXPR uint32_t get_IB0_AO_READY_C0() const { - uint32_t value = static_cast<uint32_t>(cmd_end_reached); + uint32_t value = static_cast<uint32_t>(IB0_AO_READY_C0); return value; } - uint32_t get_cmd_end_reached() const volatile + uint32_t get_IB0_AO_READY_C0() const volatile { - uint32_t value = static_cast<uint32_t>(cmd_end_reached); + uint32_t value = static_cast<uint32_t>(IB0_AO_READY_C0); return value; } - CONSTEXPR status_r &set_cmd_end_reached(uint32_t value) + CONSTEXPR dma_status0_r &set_IB0_AO_READY_C0(uint32_t value) { - cmd_end_reached = ((1u << 1) - 1) & static_cast<uint32_t>(value); + IB0_AO_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_pmu_irq_raised() const + CONSTEXPR uint32_t get_IB1_AO_VALID_C0() const { - uint32_t value = static_cast<uint32_t>(pmu_irq_raised); + uint32_t value = static_cast<uint32_t>(IB1_AO_VALID_C0); return value; } - uint32_t get_pmu_irq_raised() const volatile + uint32_t get_IB1_AO_VALID_C0() const volatile { - uint32_t value = static_cast<uint32_t>(pmu_irq_raised); + uint32_t value = static_cast<uint32_t>(IB1_AO_VALID_C0); return value; } - CONSTEXPR status_r &set_pmu_irq_raised(uint32_t value) + CONSTEXPR dma_status0_r &set_IB1_AO_VALID_C0(uint32_t value) { - pmu_irq_raised = ((1u << 1) - 1) & static_cast<uint32_t>(value); + IB1_AO_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_wd_fault() const + CONSTEXPR uint32_t get_IB1_AO_READY_C0() const { - uint32_t value = static_cast<uint32_t>(wd_fault); + uint32_t value = static_cast<uint32_t>(IB1_AO_READY_C0); return value; } - uint32_t get_wd_fault() const volatile + uint32_t get_IB1_AO_READY_C0() const volatile { - uint32_t value = static_cast<uint32_t>(wd_fault); + uint32_t value = static_cast<uint32_t>(IB1_AO_READY_C0); return value; } - CONSTEXPR status_r &set_wd_fault(uint32_t value) + CONSTEXPR dma_status0_r &set_IB1_AO_READY_C0(uint32_t value) { - wd_fault = ((1u << 1) - 1) & static_cast<uint32_t>(value); + IB1_AO_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_faulting_interface() const + CONSTEXPR uint32_t get_OB0_VALID_C0() const { - uint32_t value = static_cast<uint32_t>(faulting_interface); + uint32_t value = static_cast<uint32_t>(OB0_VALID_C0); return value; } - uint32_t get_faulting_interface() const volatile + uint32_t get_OB0_VALID_C0() const volatile { - uint32_t value = static_cast<uint32_t>(faulting_interface); + uint32_t value = static_cast<uint32_t>(OB0_VALID_C0); return value; } - CONSTEXPR status_r &set_faulting_interface(uint32_t value) + CONSTEXPR dma_status0_r &set_OB0_VALID_C0(uint32_t value) { - faulting_interface = ((1u << 1) - 1) & static_cast<uint32_t>(value); + OB0_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_faulting_channel() const + CONSTEXPR uint32_t get_OB0_READY_C0() const { - uint32_t value = static_cast<uint32_t>(faulting_channel); + uint32_t value = static_cast<uint32_t>(OB0_READY_C0); return value; } - uint32_t get_faulting_channel() const volatile + uint32_t get_OB0_READY_C0() const volatile { - uint32_t value = static_cast<uint32_t>(faulting_channel); + uint32_t value = static_cast<uint32_t>(OB0_READY_C0); return value; } - CONSTEXPR status_r &set_faulting_channel(uint32_t value) + CONSTEXPR dma_status0_r &set_OB0_READY_C0(uint32_t value) { - faulting_channel = ((1u << 4) - 1) & static_cast<uint32_t>(value); + OB0_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_irq_history_mask() const + CONSTEXPR uint32_t get_OB1_VALID_C0() const { - uint32_t value = static_cast<uint32_t>(irq_history_mask); + uint32_t value = static_cast<uint32_t>(OB1_VALID_C0); return value; } - uint32_t get_irq_history_mask() const volatile + uint32_t get_OB1_VALID_C0() const volatile { - uint32_t value = static_cast<uint32_t>(irq_history_mask); + uint32_t value = static_cast<uint32_t>(OB1_VALID_C0); return value; } - CONSTEXPR status_r &set_irq_history_mask(uint32_t value) + CONSTEXPR dma_status0_r &set_OB1_VALID_C0(uint32_t value) { - irq_history_mask = ((1u << 16) - 1) & static_cast<uint32_t>(value); + OB1_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// cmd_r - Command register, reads as last written command -struct cmd_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_OB1_READY_C0() const { - struct - { - uint32_t transition_to_running_state : 1; // Write 1 to transition the NPU to running state. Writing 0 has - // no effect - uint32_t clear_irq : 1; // Write 1 to clear the IRQ status in the STATUS register. Writing 0 has no effect - uint32_t clock_q_enable : 1; // Write 1 to this bit to enable clock off using clock q-interface and enable - // the master clock gate - uint32_t power_q_enable : 1; // Write 1 to this bit to enable power off using power q-interface - uint32_t - stop_request : 1; // Write 1 to this bit to request STOP after completing any already-started commands - uint32_t reserved0 : 11; - uint32_t clear_irq_history : 16; // Clears the IRQ history mask - }; - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR cmd_r() : - transition_to_running_state(static_cast<uint32_t>(0x0)), clear_irq(static_cast<uint32_t>(0x0)), - clock_q_enable(static_cast<uint32_t>(0x0)), power_q_enable(static_cast<uint32_t>(0x0)), - stop_request(static_cast<uint32_t>(0x0)), reserved0(static_cast<uint32_t>(0)), - clear_irq_history(static_cast<uint32_t>(0x0)) + uint32_t value = static_cast<uint32_t>(OB1_READY_C0); + return value; + } + uint32_t get_OB1_READY_C0() const volatile { + uint32_t value = static_cast<uint32_t>(OB1_READY_C0); + return value; } - CONSTEXPR cmd_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + CONSTEXPR dma_status0_r &set_OB1_READY_C0(uint32_t value) { - word = value; + OB1_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - void operator=(uint32_t value) volatile + CONSTEXPR uint32_t get_CMD_VALID() const { - word = value; + uint32_t value = static_cast<uint32_t>(CMD_VALID); + return value; } - CONSTEXPR operator uint32_t() + uint32_t get_CMD_VALID() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(CMD_VALID); + return value; } - operator uint32_t() volatile + CONSTEXPR dma_status0_r &set_CMD_VALID(uint32_t value) { - return word; + CMD_VALID = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - cmd_r copy() volatile + CONSTEXPR uint32_t get_CMD_READY() const + { + uint32_t value = static_cast<uint32_t>(CMD_READY); + return value; + } + uint32_t get_CMD_READY() const volatile { + uint32_t value = static_cast<uint32_t>(CMD_READY); + return value; + } + CONSTEXPR dma_status0_r &set_CMD_READY(uint32_t value) + { + CMD_READY = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_transition_to_running_state() const + CONSTEXPR uint32_t get_WD_BITSTREAM_VALID_C0() const { - uint32_t value = static_cast<uint32_t>(transition_to_running_state); + uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_VALID_C0); return value; } - uint32_t get_transition_to_running_state() const volatile + uint32_t get_WD_BITSTREAM_VALID_C0() const volatile { - uint32_t value = static_cast<uint32_t>(transition_to_running_state); + uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_VALID_C0); return value; } - CONSTEXPR cmd_r &set_transition_to_running_state(uint32_t value) + CONSTEXPR dma_status0_r &set_WD_BITSTREAM_VALID_C0(uint32_t value) { - transition_to_running_state = ((1u << 1) - 1) & static_cast<uint32_t>(value); + WD_BITSTREAM_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_clear_irq() const + CONSTEXPR uint32_t get_WD_BITSTREAM_READY_C0() const { - uint32_t value = static_cast<uint32_t>(clear_irq); + uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_READY_C0); return value; } - uint32_t get_clear_irq() const volatile + uint32_t get_WD_BITSTREAM_READY_C0() const volatile { - uint32_t value = static_cast<uint32_t>(clear_irq); + uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_READY_C0); return value; } - CONSTEXPR cmd_r &set_clear_irq(uint32_t value) + CONSTEXPR dma_status0_r &set_WD_BITSTREAM_READY_C0(uint32_t value) { - clear_irq = ((1u << 1) - 1) & static_cast<uint32_t>(value); + WD_BITSTREAM_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_clock_q_enable() const + CONSTEXPR uint32_t get_BS_BITSTREAM_VALID_C0() const { - uint32_t value = static_cast<uint32_t>(clock_q_enable); + uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_VALID_C0); return value; } - uint32_t get_clock_q_enable() const volatile + uint32_t get_BS_BITSTREAM_VALID_C0() const volatile { - uint32_t value = static_cast<uint32_t>(clock_q_enable); + uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_VALID_C0); return value; } - CONSTEXPR cmd_r &set_clock_q_enable(uint32_t value) + CONSTEXPR dma_status0_r &set_BS_BITSTREAM_VALID_C0(uint32_t value) { - clock_q_enable = ((1u << 1) - 1) & static_cast<uint32_t>(value); + BS_BITSTREAM_VALID_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_power_q_enable() const + CONSTEXPR uint32_t get_BS_BITSTREAM_READY_C0() const { - uint32_t value = static_cast<uint32_t>(power_q_enable); + uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_READY_C0); return value; } - uint32_t get_power_q_enable() const volatile + uint32_t get_BS_BITSTREAM_READY_C0() const volatile { - uint32_t value = static_cast<uint32_t>(power_q_enable); + uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_READY_C0); return value; } - CONSTEXPR cmd_r &set_power_q_enable(uint32_t value) + CONSTEXPR dma_status0_r &set_BS_BITSTREAM_READY_C0(uint32_t value) { - power_q_enable = ((1u << 1) - 1) & static_cast<uint32_t>(value); + BS_BITSTREAM_READY_C0 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_stop_request() const + CONSTEXPR uint32_t get_AXI0_AR_STALLED() const { - uint32_t value = static_cast<uint32_t>(stop_request); + uint32_t value = static_cast<uint32_t>(AXI0_AR_STALLED); return value; } - uint32_t get_stop_request() const volatile + uint32_t get_AXI0_AR_STALLED() const volatile { - uint32_t value = static_cast<uint32_t>(stop_request); + uint32_t value = static_cast<uint32_t>(AXI0_AR_STALLED); return value; } - CONSTEXPR cmd_r &set_stop_request(uint32_t value) + CONSTEXPR dma_status0_r &set_AXI0_AR_STALLED(uint32_t value) { - stop_request = ((1u << 1) - 1) & static_cast<uint32_t>(value); + AXI0_AR_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_clear_irq_history() const + CONSTEXPR uint32_t get_AXI0_RD_LIMIT_STALL() const { - uint32_t value = static_cast<uint32_t>(clear_irq_history); + uint32_t value = static_cast<uint32_t>(AXI0_RD_LIMIT_STALL); return value; } - uint32_t get_clear_irq_history() const volatile + uint32_t get_AXI0_RD_LIMIT_STALL() const volatile { - uint32_t value = static_cast<uint32_t>(clear_irq_history); + uint32_t value = static_cast<uint32_t>(AXI0_RD_LIMIT_STALL); return value; } - CONSTEXPR cmd_r &set_clear_irq_history(uint32_t value) + CONSTEXPR dma_status0_r &set_AXI0_RD_LIMIT_STALL(uint32_t value) { - clear_irq_history = ((1u << 16) - 1) & static_cast<uint32_t>(value); + AXI0_RD_LIMIT_STALL = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_AXI0_AW_STALLED() const + { + uint32_t value = static_cast<uint32_t>(AXI0_AW_STALLED); + return value; + } + uint32_t get_AXI0_AW_STALLED() const volatile + { + uint32_t value = static_cast<uint32_t>(AXI0_AW_STALLED); + return value; + } + CONSTEXPR dma_status0_r &set_AXI0_AW_STALLED(uint32_t value) + { + AXI0_AW_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_AXI0_W_STALLED() const + { + uint32_t value = static_cast<uint32_t>(AXI0_W_STALLED); + return value; + } + uint32_t get_AXI0_W_STALLED() const volatile + { + uint32_t value = static_cast<uint32_t>(AXI0_W_STALLED); + return value; + } + CONSTEXPR dma_status0_r &set_AXI0_W_STALLED(uint32_t value) + { + AXI0_W_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// reset_r - Request Reset and new security mode -struct reset_r +// dma_status1_r - DMA_STATUS1 of core DEBUGCORE +struct dma_status1_r { #ifdef __cplusplus private: @@ -5128,20 +5120,55 @@ struct reset_r { struct { - uint32_t pending_CPL : 1; // Current privilege level 0=User 1=Privileged - uint32_t pending_CSL : 1; // Current security level 0=Secure 1=Non secure - uint32_t reserved0 : 30; + uint32_t AXI0_WR_LIMIT_STALL : 1; // Write stalled due to one AXI0 limit counter being reached + uint32_t AXI1_AR_STALLED : 1; // Read transfer request stalled on arready low AXI1 (due to memory system) + uint32_t AXI1_RD_LIMIT_STALL : 1; // Read stalled due to one AXI1 limit counter being reached + uint32_t AXI1_WR_STALLED : 1; // Write transfer request stalled on awready low AXI1 (due to memory system) + uint32_t AXI1_W_STALLED : 1; // Write transfer stalled on wready low AXI1 (due to memory system) + uint32_t AXI1_WR_LIMIT_STALL : 1; // Write stalled due to one AXI1 limit counter being reached + uint32_t WGT_IDLE_C1 : 1; // When this bit is high means that the WGT block is not busy in generating + // addresses for a WGT job + uint32_t BAS_IDLE_C1 : 1; // When this bit is high means that the BAS block is not busy in generating + // addresses for a BAS job. + uint32_t IB0_AI_VALID_C1 : 1; // Data for AI to be read in IFM input buffer 0 - Core 1 + uint32_t IB0_AI_READY_C1 : 1; // Data consumed from AI in IFM input buffer 0 - Core 1 + uint32_t IB1_AI_VALID_C1 : 1; // Data for AI to be read in IFM input buffer 1 - Core 1 + uint32_t IB1_AI_READY_C1 : 1; // Data consumed from AI in IFM input buffer 1 - Core 1 + uint32_t IB0_AO_VALID_C1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1 + uint32_t IB0_AO_READY_C1 : 1; // Data consumed from AO in IFM input buffer 0 - Core 1 + uint32_t IB1_AO_VALID_C1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1 + uint32_t IB1_AO_READY_C1 : 1; // Data consumed from AO in IFM input buffer 1 - Core 1 + uint32_t OB0_VALID_C1 : 1; // Data for DMA ready to be consumed in OFM output buffer 0 - Core 1 + uint32_t OB0_READY_C1 : 1; // Data consumed from DMA in OFM output buffer 0 - Core 1 + uint32_t OB1_VALID_C1 : 1; // Data for DMA ready to be consumed in OFM output buffer 1 - Core 1 + uint32_t OB1_READY_C1 : 1; // Data consumed from DMA in OFM output buffer 1 - Core 1 + uint32_t WD_BITSTREAM_VALID_C1 : 1; // New weight word for WD to be consumed - Core 1 + uint32_t WD_BITSTREAM_READY_C1 : 1; // Weight word consumed by WD - Core 1 + uint32_t BS_BITSTREAM_VALID_C1 : 1; // New BaS word for AO to be consumed - Core 1 + uint32_t BS_BITSTREAM_READY_C1 : 1; // BaS word consumed by AO - Core 1 + uint32_t reserved0 : 8; }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR reset_r() : - pending_CPL(static_cast<uint32_t>(::privilege_level::USER)), - pending_CSL(static_cast<uint32_t>(::security_level::SECURE)), reserved0(static_cast<uint32_t>(0)) + CONSTEXPR dma_status1_r() : + AXI0_WR_LIMIT_STALL(static_cast<uint32_t>(0)), AXI1_AR_STALLED(static_cast<uint32_t>(0)), + AXI1_RD_LIMIT_STALL(static_cast<uint32_t>(0)), AXI1_WR_STALLED(static_cast<uint32_t>(0)), + AXI1_W_STALLED(static_cast<uint32_t>(0)), AXI1_WR_LIMIT_STALL(static_cast<uint32_t>(0)), + WGT_IDLE_C1(static_cast<uint32_t>(0)), BAS_IDLE_C1(static_cast<uint32_t>(0)), + IB0_AI_VALID_C1(static_cast<uint32_t>(0)), IB0_AI_READY_C1(static_cast<uint32_t>(0)), + IB1_AI_VALID_C1(static_cast<uint32_t>(0)), IB1_AI_READY_C1(static_cast<uint32_t>(0)), + IB0_AO_VALID_C1(static_cast<uint32_t>(0)), IB0_AO_READY_C1(static_cast<uint32_t>(0)), + IB1_AO_VALID_C1(static_cast<uint32_t>(0)), IB1_AO_READY_C1(static_cast<uint32_t>(0)), + OB0_VALID_C1(static_cast<uint32_t>(0)), OB0_READY_C1(static_cast<uint32_t>(0)), + OB1_VALID_C1(static_cast<uint32_t>(0)), OB1_READY_C1(static_cast<uint32_t>(0)), + WD_BITSTREAM_VALID_C1(static_cast<uint32_t>(0)), WD_BITSTREAM_READY_C1(static_cast<uint32_t>(0)), + BS_BITSTREAM_VALID_C1(static_cast<uint32_t>(0)), BS_BITSTREAM_READY_C1(static_cast<uint32_t>(0)), + reserved0(static_cast<uint32_t>(0)) { } - CONSTEXPR reset_r(uint32_t init) : word(init) {} + CONSTEXPR dma_status1_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -5158,387 +5185,375 @@ struct reset_r { return word; } - reset_r copy() volatile + dma_status1_r copy() volatile { return *this; } - CONSTEXPR ::privilege_level get_pending_CPL() const + CONSTEXPR uint32_t get_AXI0_WR_LIMIT_STALL() const { - ::privilege_level value = static_cast<::privilege_level>(pending_CPL); + uint32_t value = static_cast<uint32_t>(AXI0_WR_LIMIT_STALL); return value; } - ::privilege_level get_pending_CPL() const volatile + uint32_t get_AXI0_WR_LIMIT_STALL() const volatile { - ::privilege_level value = static_cast<::privilege_level>(pending_CPL); + uint32_t value = static_cast<uint32_t>(AXI0_WR_LIMIT_STALL); return value; } - CONSTEXPR reset_r &set_pending_CPL(::privilege_level value) + CONSTEXPR dma_status1_r &set_AXI0_WR_LIMIT_STALL(uint32_t value) { - pending_CPL = ((1u << 1) - 1) & static_cast<uint32_t>(value); + AXI0_WR_LIMIT_STALL = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR ::security_level get_pending_CSL() const + CONSTEXPR uint32_t get_AXI1_AR_STALLED() const { - ::security_level value = static_cast<::security_level>(pending_CSL); + uint32_t value = static_cast<uint32_t>(AXI1_AR_STALLED); return value; } - ::security_level get_pending_CSL() const volatile + uint32_t get_AXI1_AR_STALLED() const volatile { - ::security_level value = static_cast<::security_level>(pending_CSL); + uint32_t value = static_cast<uint32_t>(AXI1_AR_STALLED); return value; } - CONSTEXPR reset_r &set_pending_CSL(::security_level value) + CONSTEXPR dma_status1_r &set_AXI1_AR_STALLED(uint32_t value) { - pending_CSL = ((1u << 1) - 1) & static_cast<uint32_t>(value); + AXI1_AR_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// qbase0_r - Base address of command queue bits [31:0]. The address is 4 byte aligned -struct qbase0_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_AXI1_RD_LIMIT_STALL() const { - uint32_t QBASE0; // The 4 byte aligned lower bytes of the base address value for the command stream - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR qbase0_r() : QBASE0(static_cast<uint32_t>(0x00000000)) {} - CONSTEXPR qbase0_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(AXI1_RD_LIMIT_STALL); + return value; + } + uint32_t get_AXI1_RD_LIMIT_STALL() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(AXI1_RD_LIMIT_STALL); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR dma_status1_r &set_AXI1_RD_LIMIT_STALL(uint32_t value) { - word = value; + AXI1_RD_LIMIT_STALL = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_AXI1_WR_STALLED() const { - return word; + uint32_t value = static_cast<uint32_t>(AXI1_WR_STALLED); + return value; } - operator uint32_t() volatile + uint32_t get_AXI1_WR_STALLED() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(AXI1_WR_STALLED); + return value; } - qbase0_r copy() volatile + CONSTEXPR dma_status1_r &set_AXI1_WR_STALLED(uint32_t value) { + AXI1_WR_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_QBASE0() const + CONSTEXPR uint32_t get_AXI1_W_STALLED() const { - uint32_t value = static_cast<uint32_t>(QBASE0); + uint32_t value = static_cast<uint32_t>(AXI1_W_STALLED); return value; } - uint32_t get_QBASE0() const volatile + uint32_t get_AXI1_W_STALLED() const volatile { - uint32_t value = static_cast<uint32_t>(QBASE0); + uint32_t value = static_cast<uint32_t>(AXI1_W_STALLED); return value; } - CONSTEXPR qbase0_r &set_QBASE0(uint32_t value) + CONSTEXPR dma_status1_r &set_AXI1_W_STALLED(uint32_t value) { - QBASE0 = static_cast<uint32_t>(value); + AXI1_W_STALLED = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// qbase1_r - Address extension bits [47:32] bits for queue base -struct qbase1_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_AXI1_WR_LIMIT_STALL() const { - uint32_t QBASE1; // The 4 byte aligned upper bytes of the base address value for the command stream - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR qbase1_r() : QBASE1(static_cast<uint32_t>(0x00000000)) {} - CONSTEXPR qbase1_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(AXI1_WR_LIMIT_STALL); + return value; + } + uint32_t get_AXI1_WR_LIMIT_STALL() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(AXI1_WR_LIMIT_STALL); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR dma_status1_r &set_AXI1_WR_LIMIT_STALL(uint32_t value) { - word = value; + AXI1_WR_LIMIT_STALL = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_WGT_IDLE_C1() const { - return word; + uint32_t value = static_cast<uint32_t>(WGT_IDLE_C1); + return value; } - operator uint32_t() volatile + uint32_t get_WGT_IDLE_C1() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(WGT_IDLE_C1); + return value; } - qbase1_r copy() volatile + CONSTEXPR dma_status1_r &set_WGT_IDLE_C1(uint32_t value) { + WGT_IDLE_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_QBASE1() const + CONSTEXPR uint32_t get_BAS_IDLE_C1() const { - uint32_t value = static_cast<uint32_t>(QBASE1); + uint32_t value = static_cast<uint32_t>(BAS_IDLE_C1); return value; } - uint32_t get_QBASE1() const volatile + uint32_t get_BAS_IDLE_C1() const volatile { - uint32_t value = static_cast<uint32_t>(QBASE1); + uint32_t value = static_cast<uint32_t>(BAS_IDLE_C1); return value; } - CONSTEXPR qbase1_r &set_QBASE1(uint32_t value) + CONSTEXPR dma_status1_r &set_BAS_IDLE_C1(uint32_t value) { - QBASE1 = static_cast<uint32_t>(value); + BAS_IDLE_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// qread_r - Read offset in the command stream in bytes. Multiple of 4 in the range 0 to 16 MB -struct qread_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_IB0_AI_VALID_C1() const { - uint32_t QREAD; // The read offset of the current command under execution - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR qread_r() : QREAD(static_cast<uint32_t>(0x00000000)) {} - CONSTEXPR qread_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(IB0_AI_VALID_C1); + return value; + } + uint32_t get_IB0_AI_VALID_C1() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(IB0_AI_VALID_C1); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR dma_status1_r &set_IB0_AI_VALID_C1(uint32_t value) { - word = value; + IB0_AI_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_IB0_AI_READY_C1() const { - return word; + uint32_t value = static_cast<uint32_t>(IB0_AI_READY_C1); + return value; } - operator uint32_t() volatile + uint32_t get_IB0_AI_READY_C1() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(IB0_AI_READY_C1); + return value; } - qread_r copy() volatile + CONSTEXPR dma_status1_r &set_IB0_AI_READY_C1(uint32_t value) { + IB0_AI_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_QREAD() const + CONSTEXPR uint32_t get_IB1_AI_VALID_C1() const { - uint32_t value = static_cast<uint32_t>(QREAD); + uint32_t value = static_cast<uint32_t>(IB1_AI_VALID_C1); return value; } - uint32_t get_QREAD() const volatile + uint32_t get_IB1_AI_VALID_C1() const volatile { - uint32_t value = static_cast<uint32_t>(QREAD); + uint32_t value = static_cast<uint32_t>(IB1_AI_VALID_C1); return value; } - CONSTEXPR qread_r &set_QREAD(uint32_t value) + CONSTEXPR dma_status1_r &set_IB1_AI_VALID_C1(uint32_t value) { - QREAD = static_cast<uint32_t>(value); + IB1_AI_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// qconfig_r - AXI configuration for the command stream in the range 0-3. Same encoding as for REGIONCFG -struct qconfig_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_IB1_AI_READY_C1() const { - uint32_t QCONFIG; // AXI configuration for the command stream in the range 0-3 - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR qconfig_r() : QCONFIG(static_cast<uint32_t>(0x00000000)) {} - CONSTEXPR qconfig_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(IB1_AI_READY_C1); + return value; + } + uint32_t get_IB1_AI_READY_C1() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(IB1_AI_READY_C1); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR dma_status1_r &set_IB1_AI_READY_C1(uint32_t value) { - word = value; + IB1_AI_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_IB0_AO_VALID_C1() const { - return word; + uint32_t value = static_cast<uint32_t>(IB0_AO_VALID_C1); + return value; } - operator uint32_t() volatile + uint32_t get_IB0_AO_VALID_C1() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(IB0_AO_VALID_C1); + return value; } - qconfig_r copy() volatile + CONSTEXPR dma_status1_r &set_IB0_AO_VALID_C1(uint32_t value) { + IB0_AO_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_QCONFIG() const + CONSTEXPR uint32_t get_IB0_AO_READY_C1() const { - uint32_t value = static_cast<uint32_t>(QCONFIG); + uint32_t value = static_cast<uint32_t>(IB0_AO_READY_C1); return value; } - uint32_t get_QCONFIG() const volatile + uint32_t get_IB0_AO_READY_C1() const volatile { - uint32_t value = static_cast<uint32_t>(QCONFIG); + uint32_t value = static_cast<uint32_t>(IB0_AO_READY_C1); return value; } - CONSTEXPR qconfig_r &set_QCONFIG(uint32_t value) + CONSTEXPR dma_status1_r &set_IB0_AO_READY_C1(uint32_t value) { - QCONFIG = static_cast<uint32_t>(value); + IB0_AO_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// qsize_r - Size of the command stream in bytes. Multiple of 4 in the range 0 to 16 MB -struct qsize_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_IB1_AO_VALID_C1() const { - uint32_t QSIZE; // Size of the next command stream to be executed by the NPU - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR qsize_r() : QSIZE(static_cast<uint32_t>(0x00000000)) {} - CONSTEXPR qsize_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + uint32_t value = static_cast<uint32_t>(IB1_AO_VALID_C1); + return value; + } + uint32_t get_IB1_AO_VALID_C1() const volatile { - word = value; + uint32_t value = static_cast<uint32_t>(IB1_AO_VALID_C1); + return value; } - void operator=(uint32_t value) volatile + CONSTEXPR dma_status1_r &set_IB1_AO_VALID_C1(uint32_t value) { - word = value; + IB1_AO_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - CONSTEXPR operator uint32_t() + CONSTEXPR uint32_t get_IB1_AO_READY_C1() const { - return word; + uint32_t value = static_cast<uint32_t>(IB1_AO_READY_C1); + return value; } - operator uint32_t() volatile + uint32_t get_IB1_AO_READY_C1() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(IB1_AO_READY_C1); + return value; } - qsize_r copy() volatile + CONSTEXPR dma_status1_r &set_IB1_AO_READY_C1(uint32_t value) { + IB1_AO_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_QSIZE() const + CONSTEXPR uint32_t get_OB0_VALID_C1() const { - uint32_t value = static_cast<uint32_t>(QSIZE); + uint32_t value = static_cast<uint32_t>(OB0_VALID_C1); return value; } - uint32_t get_QSIZE() const volatile + uint32_t get_OB0_VALID_C1() const volatile { - uint32_t value = static_cast<uint32_t>(QSIZE); + uint32_t value = static_cast<uint32_t>(OB0_VALID_C1); return value; } - CONSTEXPR qsize_r &set_QSIZE(uint32_t value) + CONSTEXPR dma_status1_r &set_OB0_VALID_C1(uint32_t value) { - QSIZE = static_cast<uint32_t>(value); + OB0_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } -#endif //__cplusplus -}; - -// prot_r - Protection level configured for the NPU when acting as an AXI master -struct prot_r -{ -#ifdef __cplusplus - private: -#endif //__cplusplus - union + CONSTEXPR uint32_t get_OB0_READY_C1() const { - struct - { - uint32_t active_CPL : 1; // Current privilege level 0=User 1=Privileged - uint32_t active_CSL : 1; // Current security level 0=Secure 1=Non secure - uint32_t reserved0 : 30; - }; - uint32_t word; - }; -#ifdef __cplusplus - public: - CONSTEXPR prot_r() : - active_CPL(static_cast<uint32_t>(::privilege_level::USER)), - active_CSL(static_cast<uint32_t>(::security_level::SECURE)), reserved0(static_cast<uint32_t>(0)) + uint32_t value = static_cast<uint32_t>(OB0_READY_C1); + return value; + } + uint32_t get_OB0_READY_C1() const volatile { + uint32_t value = static_cast<uint32_t>(OB0_READY_C1); + return value; } - CONSTEXPR prot_r(uint32_t init) : word(init) {} - CONSTEXPR void operator=(uint32_t value) + CONSTEXPR dma_status1_r &set_OB0_READY_C1(uint32_t value) { - word = value; + OB0_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - void operator=(uint32_t value) volatile + CONSTEXPR uint32_t get_OB1_VALID_C1() const { - word = value; + uint32_t value = static_cast<uint32_t>(OB1_VALID_C1); + return value; } - CONSTEXPR operator uint32_t() + uint32_t get_OB1_VALID_C1() const volatile { - return word; + uint32_t value = static_cast<uint32_t>(OB1_VALID_C1); + return value; } - operator uint32_t() volatile + CONSTEXPR dma_status1_r &set_OB1_VALID_C1(uint32_t value) { - return word; + OB1_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; } - prot_r copy() volatile + CONSTEXPR uint32_t get_OB1_READY_C1() const { + uint32_t value = static_cast<uint32_t>(OB1_READY_C1); + return value; + } + uint32_t get_OB1_READY_C1() const volatile + { + uint32_t value = static_cast<uint32_t>(OB1_READY_C1); + return value; + } + CONSTEXPR dma_status1_r &set_OB1_READY_C1(uint32_t value) + { + OB1_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR ::privilege_level get_active_CPL() const + CONSTEXPR uint32_t get_WD_BITSTREAM_VALID_C1() const { - ::privilege_level value = static_cast<::privilege_level>(active_CPL); + uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_VALID_C1); return value; } - ::privilege_level get_active_CPL() const volatile + uint32_t get_WD_BITSTREAM_VALID_C1() const volatile { - ::privilege_level value = static_cast<::privilege_level>(active_CPL); + uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_VALID_C1); return value; } - CONSTEXPR prot_r &set_active_CPL(::privilege_level value) + CONSTEXPR dma_status1_r &set_WD_BITSTREAM_VALID_C1(uint32_t value) { - active_CPL = ((1u << 1) - 1) & static_cast<uint32_t>(value); + WD_BITSTREAM_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR ::security_level get_active_CSL() const + CONSTEXPR uint32_t get_WD_BITSTREAM_READY_C1() const { - ::security_level value = static_cast<::security_level>(active_CSL); + uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_READY_C1); return value; } - ::security_level get_active_CSL() const volatile + uint32_t get_WD_BITSTREAM_READY_C1() const volatile { - ::security_level value = static_cast<::security_level>(active_CSL); + uint32_t value = static_cast<uint32_t>(WD_BITSTREAM_READY_C1); return value; } - CONSTEXPR prot_r &set_active_CSL(::security_level value) + CONSTEXPR dma_status1_r &set_WD_BITSTREAM_READY_C1(uint32_t value) { - active_CSL = ((1u << 1) - 1) & static_cast<uint32_t>(value); + WD_BITSTREAM_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_BS_BITSTREAM_VALID_C1() const + { + uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_VALID_C1); + return value; + } + uint32_t get_BS_BITSTREAM_VALID_C1() const volatile + { + uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_VALID_C1); + return value; + } + CONSTEXPR dma_status1_r &set_BS_BITSTREAM_VALID_C1(uint32_t value) + { + BS_BITSTREAM_VALID_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_BS_BITSTREAM_READY_C1() const + { + uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_READY_C1); + return value; + } + uint32_t get_BS_BITSTREAM_READY_C1() const volatile + { + uint32_t value = static_cast<uint32_t>(BS_BITSTREAM_READY_C1); + return value; + } + CONSTEXPR dma_status1_r &set_BS_BITSTREAM_READY_C1(uint32_t value) + { + BS_BITSTREAM_READY_C1 = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// config_r - RTL configuration -struct config_r +// clkforce_r - Force clocks on for clock gating +struct clkforce_r { #ifdef __cplusplus private: @@ -5547,23 +5562,25 @@ struct config_r { struct { - uint32_t macs_per_cc : 4; // The log2(macs/clock cycle). Valid encoding range is 5 to 8 for 32 to 256 - // MACs/clock cycle. - uint32_t cmd_stream_version : 4; // command stream version accepted by this NPU. Set to 0 for Ethos-U55 EAC. - uint32_t shram_size : 8; // Size in KB of SHRAM in the range 8 to 48. - uint32_t reserved0 : 12; - uint32_t product : 4; // Product configuration + uint32_t top_level_clk : 1; // set to 1 to force on TOP level clock + uint32_t cc_clk : 1; // set to 1 to force on CC clock + uint32_t dma_clk : 1; // set to 1 to force on DMA clock + uint32_t mac_clk : 1; // set to 1 to force on MAC clock + uint32_t ao_clk : 1; // set to 1 to force on AO clock + uint32_t wd_clk : 1; // set to 1 to force on WD clock + uint32_t reserved0 : 26; }; uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR config_r() : - macs_per_cc(static_cast<uint32_t>(0)), cmd_stream_version(static_cast<uint32_t>(0x0)), - shram_size(static_cast<uint32_t>(0)), reserved0(static_cast<uint32_t>(0)), product(static_cast<uint32_t>(0)) + CONSTEXPR clkforce_r() : + top_level_clk(static_cast<uint32_t>(0)), cc_clk(static_cast<uint32_t>(0)), dma_clk(static_cast<uint32_t>(0)), + mac_clk(static_cast<uint32_t>(0)), ao_clk(static_cast<uint32_t>(0)), wd_clk(static_cast<uint32_t>(0)), + reserved0(static_cast<uint32_t>(0)) { } - CONSTEXPR config_r(uint32_t init) : word(init) {} + CONSTEXPR clkforce_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -5580,88 +5597,118 @@ struct config_r { return word; } - config_r copy() volatile + clkforce_r copy() volatile { return *this; } - CONSTEXPR ::macs_per_cc get_macs_per_cc() const + CONSTEXPR uint32_t get_top_level_clk() const { - ::macs_per_cc value = static_cast<::macs_per_cc>(macs_per_cc); + uint32_t value = static_cast<uint32_t>(top_level_clk); return value; } - ::macs_per_cc get_macs_per_cc() const volatile + uint32_t get_top_level_clk() const volatile { - ::macs_per_cc value = static_cast<::macs_per_cc>(macs_per_cc); + uint32_t value = static_cast<uint32_t>(top_level_clk); return value; } - CONSTEXPR config_r &set_macs_per_cc(::macs_per_cc value) + CONSTEXPR clkforce_r &set_top_level_clk(uint32_t value) { - macs_per_cc = ((1u << 4) - 1) & static_cast<uint32_t>(value); + top_level_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_cmd_stream_version() const + CONSTEXPR uint32_t get_cc_clk() const { - uint32_t value = static_cast<uint32_t>(cmd_stream_version); + uint32_t value = static_cast<uint32_t>(cc_clk); return value; } - uint32_t get_cmd_stream_version() const volatile + uint32_t get_cc_clk() const volatile { - uint32_t value = static_cast<uint32_t>(cmd_stream_version); + uint32_t value = static_cast<uint32_t>(cc_clk); return value; } - CONSTEXPR config_r &set_cmd_stream_version(uint32_t value) + CONSTEXPR clkforce_r &set_cc_clk(uint32_t value) { - cmd_stream_version = ((1u << 4) - 1) & static_cast<uint32_t>(value); + cc_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR ::shram_size get_shram_size() const + CONSTEXPR uint32_t get_dma_clk() const { - ::shram_size value = static_cast<::shram_size>(shram_size); + uint32_t value = static_cast<uint32_t>(dma_clk); return value; } - ::shram_size get_shram_size() const volatile + uint32_t get_dma_clk() const volatile { - ::shram_size value = static_cast<::shram_size>(shram_size); + uint32_t value = static_cast<uint32_t>(dma_clk); return value; } - CONSTEXPR config_r &set_shram_size(::shram_size value) + CONSTEXPR clkforce_r &set_dma_clk(uint32_t value) { - shram_size = ((1u << 8) - 1) & static_cast<uint32_t>(value); + dma_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_product() const + CONSTEXPR uint32_t get_mac_clk() const { - uint32_t value = static_cast<uint32_t>(product); + uint32_t value = static_cast<uint32_t>(mac_clk); return value; } - uint32_t get_product() const volatile + uint32_t get_mac_clk() const volatile { - uint32_t value = static_cast<uint32_t>(product); + uint32_t value = static_cast<uint32_t>(mac_clk); return value; } - CONSTEXPR config_r &set_product(uint32_t value) + CONSTEXPR clkforce_r &set_mac_clk(uint32_t value) { - product = ((1u << 4) - 1) & static_cast<uint32_t>(value); + mac_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_ao_clk() const + { + uint32_t value = static_cast<uint32_t>(ao_clk); + return value; + } + uint32_t get_ao_clk() const volatile + { + uint32_t value = static_cast<uint32_t>(ao_clk); + return value; + } + CONSTEXPR clkforce_r &set_ao_clk(uint32_t value) + { + ao_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); + return *this; + } + CONSTEXPR uint32_t get_wd_clk() const + { + uint32_t value = static_cast<uint32_t>(wd_clk); + return value; + } + uint32_t get_wd_clk() const volatile + { + uint32_t value = static_cast<uint32_t>(wd_clk); + return value; + } + CONSTEXPR clkforce_r &set_wd_clk(uint32_t value) + { + wd_clk = ((1u << 1) - 1) & static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// lock_r - Lock register. This register is designed for driver use and does not affect NPU functionality -struct lock_r +// pid4_r - Peripheral ID byte 4 (Arm=code 4) +struct pid4_r { #ifdef __cplusplus private: #endif //__cplusplus union { - uint32_t LOCK; // 32 bit value for LOCK configuration + uint32_t PID4; // Byte 4 of Peripheral ID (Lower 8 bits valid) uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR lock_r() : LOCK(static_cast<uint32_t>(0x00000000)) {} - CONSTEXPR lock_r(uint32_t init) : word(init) {} + CONSTEXPR pid4_r() : PID4(static_cast<uint32_t>(0x04)) {} + CONSTEXPR pid4_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -5678,64 +5725,43 @@ struct lock_r { return word; } - lock_r copy() volatile + pid4_r copy() volatile { return *this; } - CONSTEXPR uint32_t get_LOCK() const + CONSTEXPR uint32_t get_PID4() const { - uint32_t value = static_cast<uint32_t>(LOCK); + uint32_t value = static_cast<uint32_t>(PID4); return value; } - uint32_t get_LOCK() const volatile + uint32_t get_PID4() const volatile { - uint32_t value = static_cast<uint32_t>(LOCK); + uint32_t value = static_cast<uint32_t>(PID4); return value; } - CONSTEXPR lock_r &set_LOCK(uint32_t value) + CONSTEXPR pid4_r &set_PID4(uint32_t value) { - LOCK = static_cast<uint32_t>(value); + PID4 = static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// regioncfg_r - Base pointer configuration. Bits[2*k+1:2*k] give the memory type for REGION[k] -struct regioncfg_r +// pid5_r - Peripheral ID byte 5 (reserved) +struct pid5_r { #ifdef __cplusplus private: #endif //__cplusplus union { - struct - { - uint32_t region0 : 2; // Bits for Region0 Configurion - uint32_t region1 : 2; // Bits for Region1 Configurion - uint32_t region2 : 2; // Bits for Region2 Configurion - uint32_t region3 : 2; // Bits for Region3 Configurion - uint32_t region4 : 2; // Bits for Region4 Configurion - uint32_t region5 : 2; // Bits for Region5 Configurion - uint32_t region6 : 2; // Bits for Region6 Configurion - uint32_t region7 : 2; // Bits for Region7 Configurion - uint32_t reserved0 : 16; - }; + uint32_t PID5; // Byte 5 of Peripheral ID (Lower 8 bits valid) uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR regioncfg_r() : - region0(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), - region1(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), - region2(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), - region3(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), - region4(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), - region5(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), - region6(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), - region7(static_cast<uint32_t>(::memory_type::AXI0_OUTSTANDING_COUNTER0)), reserved0(static_cast<uint32_t>(0)) - { - } - CONSTEXPR regioncfg_r(uint32_t init) : word(init) {} + CONSTEXPR pid5_r() : PID5(static_cast<uint32_t>(0x00)) {} + CONSTEXPR pid5_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -5752,163 +5778,149 @@ struct regioncfg_r { return word; } - regioncfg_r copy() volatile - { - return *this; - } - CONSTEXPR ::memory_type get_region0() const - { - ::memory_type value = static_cast<::memory_type>(region0); - return value; - } - ::memory_type get_region0() const volatile - { - ::memory_type value = static_cast<::memory_type>(region0); - return value; - } - CONSTEXPR regioncfg_r &set_region0(::memory_type value) + pid5_r copy() volatile { - region0 = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR ::memory_type get_region1() const + CONSTEXPR uint32_t get_PID5() const { - ::memory_type value = static_cast<::memory_type>(region1); + uint32_t value = static_cast<uint32_t>(PID5); return value; } - ::memory_type get_region1() const volatile + uint32_t get_PID5() const volatile { - ::memory_type value = static_cast<::memory_type>(region1); + uint32_t value = static_cast<uint32_t>(PID5); return value; } - CONSTEXPR regioncfg_r &set_region1(::memory_type value) + CONSTEXPR pid5_r &set_PID5(uint32_t value) { - region1 = ((1u << 2) - 1) & static_cast<uint32_t>(value); + PID5 = static_cast<uint32_t>(value); return *this; } - CONSTEXPR ::memory_type get_region2() const +#endif //__cplusplus +}; + +// pid6_r - Peripheral ID byte 6 (reserved) +struct pid6_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - ::memory_type value = static_cast<::memory_type>(region2); - return value; - } - ::memory_type get_region2() const volatile + uint32_t PID6; // Byte 6 of Peripheral ID (Lower 8 bits valid) + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR pid6_r() : PID6(static_cast<uint32_t>(0x00)) {} + CONSTEXPR pid6_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - ::memory_type value = static_cast<::memory_type>(region2); - return value; + word = value; } - CONSTEXPR regioncfg_r &set_region2(::memory_type value) + void operator=(uint32_t value) volatile { - region2 = ((1u << 2) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR ::memory_type get_region3() const + CONSTEXPR operator uint32_t() { - ::memory_type value = static_cast<::memory_type>(region3); - return value; + return word; } - ::memory_type get_region3() const volatile + operator uint32_t() volatile { - ::memory_type value = static_cast<::memory_type>(region3); - return value; + return word; } - CONSTEXPR regioncfg_r &set_region3(::memory_type value) + pid6_r copy() volatile { - region3 = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR ::memory_type get_region4() const + CONSTEXPR uint32_t get_PID6() const { - ::memory_type value = static_cast<::memory_type>(region4); + uint32_t value = static_cast<uint32_t>(PID6); return value; } - ::memory_type get_region4() const volatile + uint32_t get_PID6() const volatile { - ::memory_type value = static_cast<::memory_type>(region4); + uint32_t value = static_cast<uint32_t>(PID6); return value; } - CONSTEXPR regioncfg_r &set_region4(::memory_type value) + CONSTEXPR pid6_r &set_PID6(uint32_t value) { - region4 = ((1u << 2) - 1) & static_cast<uint32_t>(value); + PID6 = static_cast<uint32_t>(value); return *this; } - CONSTEXPR ::memory_type get_region5() const +#endif //__cplusplus +}; + +// pid7_r - Peripheral ID byte 7 (reserved) +struct pid7_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - ::memory_type value = static_cast<::memory_type>(region5); - return value; - } - ::memory_type get_region5() const volatile + uint32_t PID7; // Byte 7 of Peripheral ID (Lower 8 bits valid) + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR pid7_r() : PID7(static_cast<uint32_t>(0x00)) {} + CONSTEXPR pid7_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - ::memory_type value = static_cast<::memory_type>(region5); - return value; + word = value; } - CONSTEXPR regioncfg_r &set_region5(::memory_type value) + void operator=(uint32_t value) volatile { - region5 = ((1u << 2) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR ::memory_type get_region6() const + CONSTEXPR operator uint32_t() { - ::memory_type value = static_cast<::memory_type>(region6); - return value; + return word; } - ::memory_type get_region6() const volatile + operator uint32_t() volatile { - ::memory_type value = static_cast<::memory_type>(region6); - return value; + return word; } - CONSTEXPR regioncfg_r &set_region6(::memory_type value) + pid7_r copy() volatile { - region6 = ((1u << 2) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR ::memory_type get_region7() const + CONSTEXPR uint32_t get_PID7() const { - ::memory_type value = static_cast<::memory_type>(region7); + uint32_t value = static_cast<uint32_t>(PID7); return value; } - ::memory_type get_region7() const volatile + uint32_t get_PID7() const volatile { - ::memory_type value = static_cast<::memory_type>(region7); + uint32_t value = static_cast<uint32_t>(PID7); return value; } - CONSTEXPR regioncfg_r &set_region7(::memory_type value) + CONSTEXPR pid7_r &set_PID7(uint32_t value) { - region7 = ((1u << 2) - 1) & static_cast<uint32_t>(value); + PID7 = static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// axi_limit0_r - AXI limits for port 0 counter 0 -struct axi_limit0_r +// pid0_r - Peripheral ID byte 0. This is bits[7:0] of the part number. +struct pid0_r { #ifdef __cplusplus private: #endif //__cplusplus union { - struct - { - uint32_t max_beats : 2; // Burst split alignment: 0=64 bytes, 1=128 bytes, 2=256 bytes, 3=reserved - uint32_t reserved0 : 2; - uint32_t memtype : 4; // Memtype - uint32_t reserved1 : 8; - uint32_t - max_outstanding_read_m1 : 8; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 - uint32_t max_outstanding_write_m1 : 8; // Maximum number of outstanding AXI write transactions - 1 in range - // 0 to 15 - }; + uint32_t PID0; // Byte 0 of Peripheral ID (Lower 8 bits valid) uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR axi_limit0_r() : - max_beats(static_cast<uint32_t>(0x0)), reserved0(static_cast<uint32_t>(0)), memtype(static_cast<uint32_t>(0)), - reserved1(static_cast<uint32_t>(0)), max_outstanding_read_m1(static_cast<uint32_t>(0x00)), - max_outstanding_write_m1(static_cast<uint32_t>(0x000000)) - { - } - CONSTEXPR axi_limit0_r(uint32_t init) : word(init) {} + CONSTEXPR pid0_r() : PID0(static_cast<uint32_t>(0x80)) {} + CONSTEXPR pid0_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -5925,103 +5937,97 @@ struct axi_limit0_r { return word; } - axi_limit0_r copy() volatile + pid0_r copy() volatile { return *this; } - CONSTEXPR uint32_t get_max_beats() const + CONSTEXPR uint32_t get_PID0() const { - uint32_t value = static_cast<uint32_t>(max_beats); + uint32_t value = static_cast<uint32_t>(PID0); return value; } - uint32_t get_max_beats() const volatile + uint32_t get_PID0() const volatile { - uint32_t value = static_cast<uint32_t>(max_beats); + uint32_t value = static_cast<uint32_t>(PID0); return value; } - CONSTEXPR axi_limit0_r &set_max_beats(uint32_t value) + CONSTEXPR pid0_r &set_PID0(uint32_t value) { - max_beats = ((1u << 2) - 1) & static_cast<uint32_t>(value); + PID0 = static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_memtype() const +#endif //__cplusplus +}; + +// pid1_r - Peripheral ID byte 1. This is bits[11:8] of the part number in bits[3:0], and bits[3:0] of the Arm ID in +// bits[7:4]. +struct pid1_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - uint32_t value = static_cast<uint32_t>(memtype); - return value; - } - uint32_t get_memtype() const volatile + uint32_t PID1; // Byte 1 of Peripheral ID (Lower 8 bits valid) + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR pid1_r() : PID1(static_cast<uint32_t>(0xB5)) {} + CONSTEXPR pid1_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(memtype); - return value; + word = value; } - CONSTEXPR axi_limit0_r &set_memtype(uint32_t value) + void operator=(uint32_t value) volatile { - memtype = ((1u << 4) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_max_outstanding_read_m1() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); - return value; + return word; } - uint32_t get_max_outstanding_read_m1() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); - return value; + return word; } - CONSTEXPR axi_limit0_r &set_max_outstanding_read_m1(uint32_t value) + pid1_r copy() volatile { - max_outstanding_read_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_max_outstanding_write_m1() const + CONSTEXPR uint32_t get_PID1() const { - uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); + uint32_t value = static_cast<uint32_t>(PID1); return value; } - uint32_t get_max_outstanding_write_m1() const volatile + uint32_t get_PID1() const volatile { - uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); + uint32_t value = static_cast<uint32_t>(PID1); return value; } - CONSTEXPR axi_limit0_r &set_max_outstanding_write_m1(uint32_t value) + CONSTEXPR pid1_r &set_PID1(uint32_t value) { - max_outstanding_write_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); + PID1 = static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// axi_limit1_r - AXI limits for port 0 counter 1 -struct axi_limit1_r +// pid2_r - Peripheral ID byte 2. This is bits[6:4] of the Arm ID in bits[2:0], and bit 3 indicates format B. +struct pid2_r { #ifdef __cplusplus private: #endif //__cplusplus union { - struct - { - uint32_t max_beats : 2; // Burst split alignment: 0=64 bytes, 1=128 bytes, 2=256 bytes, 3=reserved - uint32_t reserved0 : 2; - uint32_t memtype : 4; // Memtype - uint32_t reserved1 : 8; - uint32_t - max_outstanding_read_m1 : 8; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 - uint32_t max_outstanding_write_m1 : 8; // Maximum number of outstanding AXI write transactions - 1 in range - // 0 to 15 - }; + uint32_t PID2; // Byte 2 of Peripheral ID (Lower 8 bits valid) uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR axi_limit1_r() : - max_beats(static_cast<uint32_t>(0x0)), reserved0(static_cast<uint32_t>(0)), memtype(static_cast<uint32_t>(0)), - reserved1(static_cast<uint32_t>(0)), max_outstanding_read_m1(static_cast<uint32_t>(0x00)), - max_outstanding_write_m1(static_cast<uint32_t>(0x000000)) - { - } - CONSTEXPR axi_limit1_r(uint32_t init) : word(init) {} + CONSTEXPR pid2_r() : PID2(static_cast<uint32_t>(0x0B)) {} + CONSTEXPR pid2_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -6038,103 +6044,96 @@ struct axi_limit1_r { return word; } - axi_limit1_r copy() volatile + pid2_r copy() volatile { return *this; } - CONSTEXPR uint32_t get_max_beats() const + CONSTEXPR uint32_t get_PID2() const { - uint32_t value = static_cast<uint32_t>(max_beats); + uint32_t value = static_cast<uint32_t>(PID2); return value; } - uint32_t get_max_beats() const volatile + uint32_t get_PID2() const volatile { - uint32_t value = static_cast<uint32_t>(max_beats); + uint32_t value = static_cast<uint32_t>(PID2); return value; } - CONSTEXPR axi_limit1_r &set_max_beats(uint32_t value) + CONSTEXPR pid2_r &set_PID2(uint32_t value) { - max_beats = ((1u << 2) - 1) & static_cast<uint32_t>(value); + PID2 = static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_memtype() const +#endif //__cplusplus +}; + +// pid3_r - Peripheral ID byte 3. +struct pid3_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - uint32_t value = static_cast<uint32_t>(memtype); - return value; - } - uint32_t get_memtype() const volatile + uint32_t PID3; // Byte 1 of Peripheral ID (Lower 8 bits valid) + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR pid3_r() : PID3(static_cast<uint32_t>(0x0)) {} + CONSTEXPR pid3_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(memtype); - return value; + word = value; } - CONSTEXPR axi_limit1_r &set_memtype(uint32_t value) + void operator=(uint32_t value) volatile { - memtype = ((1u << 4) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_max_outstanding_read_m1() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); - return value; + return word; } - uint32_t get_max_outstanding_read_m1() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); - return value; + return word; } - CONSTEXPR axi_limit1_r &set_max_outstanding_read_m1(uint32_t value) + pid3_r copy() volatile { - max_outstanding_read_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_max_outstanding_write_m1() const + CONSTEXPR uint32_t get_PID3() const { - uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); + uint32_t value = static_cast<uint32_t>(PID3); return value; } - uint32_t get_max_outstanding_write_m1() const volatile + uint32_t get_PID3() const volatile { - uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); + uint32_t value = static_cast<uint32_t>(PID3); return value; } - CONSTEXPR axi_limit1_r &set_max_outstanding_write_m1(uint32_t value) + CONSTEXPR pid3_r &set_PID3(uint32_t value) { - max_outstanding_write_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); + PID3 = static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// axi_limit2_r - AXI limits for port 1 counter 2 -struct axi_limit2_r +// cid0_r - Component ID byte 0. +struct cid0_r { #ifdef __cplusplus private: #endif //__cplusplus union { - struct - { - uint32_t max_beats : 2; // Burst split alignment: 0=64 bytes, 1=128 bytes, 2=256 bytes, 3=reserved - uint32_t reserved0 : 2; - uint32_t memtype : 4; // Memtype - uint32_t reserved1 : 8; - uint32_t - max_outstanding_read_m1 : 8; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 - uint32_t max_outstanding_write_m1 : 8; // Maximum number of outstanding AXI write transactions - 1 in range - // 0 to 15 - }; + uint32_t CID0; // Byte 0 of Component ID (Lower 8 bits valid) uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR axi_limit2_r() : - max_beats(static_cast<uint32_t>(0x0)), reserved0(static_cast<uint32_t>(0)), memtype(static_cast<uint32_t>(0)), - reserved1(static_cast<uint32_t>(0)), max_outstanding_read_m1(static_cast<uint32_t>(0x00)), - max_outstanding_write_m1(static_cast<uint32_t>(0x000000)) - { - } - CONSTEXPR axi_limit2_r(uint32_t init) : word(init) {} + CONSTEXPR cid0_r() : CID0(static_cast<uint32_t>(0x0D)) {} + CONSTEXPR cid0_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -6151,103 +6150,96 @@ struct axi_limit2_r { return word; } - axi_limit2_r copy() volatile + cid0_r copy() volatile { return *this; } - CONSTEXPR uint32_t get_max_beats() const + CONSTEXPR uint32_t get_CID0() const { - uint32_t value = static_cast<uint32_t>(max_beats); + uint32_t value = static_cast<uint32_t>(CID0); return value; } - uint32_t get_max_beats() const volatile + uint32_t get_CID0() const volatile { - uint32_t value = static_cast<uint32_t>(max_beats); + uint32_t value = static_cast<uint32_t>(CID0); return value; } - CONSTEXPR axi_limit2_r &set_max_beats(uint32_t value) + CONSTEXPR cid0_r &set_CID0(uint32_t value) { - max_beats = ((1u << 2) - 1) & static_cast<uint32_t>(value); + CID0 = static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_memtype() const +#endif //__cplusplus +}; + +// cid1_r - Component ID byte 1. +struct cid1_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - uint32_t value = static_cast<uint32_t>(memtype); - return value; - } - uint32_t get_memtype() const volatile + uint32_t CID1; // Byte 1 of Component ID (Lower 8 bits valid) + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR cid1_r() : CID1(static_cast<uint32_t>(0xF0)) {} + CONSTEXPR cid1_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(memtype); - return value; + word = value; } - CONSTEXPR axi_limit2_r &set_memtype(uint32_t value) + void operator=(uint32_t value) volatile { - memtype = ((1u << 4) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_max_outstanding_read_m1() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); - return value; + return word; } - uint32_t get_max_outstanding_read_m1() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); - return value; + return word; } - CONSTEXPR axi_limit2_r &set_max_outstanding_read_m1(uint32_t value) + cid1_r copy() volatile { - max_outstanding_read_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_max_outstanding_write_m1() const + CONSTEXPR uint32_t get_CID1() const { - uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); + uint32_t value = static_cast<uint32_t>(CID1); return value; } - uint32_t get_max_outstanding_write_m1() const volatile + uint32_t get_CID1() const volatile { - uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); + uint32_t value = static_cast<uint32_t>(CID1); return value; } - CONSTEXPR axi_limit2_r &set_max_outstanding_write_m1(uint32_t value) + CONSTEXPR cid1_r &set_CID1(uint32_t value) { - max_outstanding_write_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); + CID1 = static_cast<uint32_t>(value); return *this; } #endif //__cplusplus }; -// axi_limit3_r - AXI limits for port 1 counter 3 -struct axi_limit3_r +// cid2_r - Component ID byte 2. +struct cid2_r { #ifdef __cplusplus private: #endif //__cplusplus union { - struct - { - uint32_t max_beats : 2; // Burst split alignment: 0=64 bytes, 1=128 bytes, 2=256 bytes, 3=reserved - uint32_t reserved0 : 2; - uint32_t memtype : 4; // Memtype - uint32_t reserved1 : 8; - uint32_t - max_outstanding_read_m1 : 8; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 - uint32_t max_outstanding_write_m1 : 8; // Maximum number of outstanding AXI write transactions - 1 in range - // 0 to 15 - }; + uint32_t CID2; // Byte 2 of Component ID (Lower 8 bits valid) uint32_t word; }; #ifdef __cplusplus public: - CONSTEXPR axi_limit3_r() : - max_beats(static_cast<uint32_t>(0x0)), reserved0(static_cast<uint32_t>(0)), memtype(static_cast<uint32_t>(0)), - reserved1(static_cast<uint32_t>(0)), max_outstanding_read_m1(static_cast<uint32_t>(0x00)), - max_outstanding_write_m1(static_cast<uint32_t>(0x000000)) - { - } - CONSTEXPR axi_limit3_r(uint32_t init) : word(init) {} + CONSTEXPR cid2_r() : CID2(static_cast<uint32_t>(0x05)) {} + CONSTEXPR cid2_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { word = value; @@ -6264,68 +6256,76 @@ struct axi_limit3_r { return word; } - axi_limit3_r copy() volatile + cid2_r copy() volatile { return *this; } - CONSTEXPR uint32_t get_max_beats() const + CONSTEXPR uint32_t get_CID2() const { - uint32_t value = static_cast<uint32_t>(max_beats); + uint32_t value = static_cast<uint32_t>(CID2); return value; } - uint32_t get_max_beats() const volatile + uint32_t get_CID2() const volatile { - uint32_t value = static_cast<uint32_t>(max_beats); + uint32_t value = static_cast<uint32_t>(CID2); return value; } - CONSTEXPR axi_limit3_r &set_max_beats(uint32_t value) + CONSTEXPR cid2_r &set_CID2(uint32_t value) { - max_beats = ((1u << 2) - 1) & static_cast<uint32_t>(value); + CID2 = static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_memtype() const +#endif //__cplusplus +}; + +// cid3_r - Component ID byte 3. +struct cid3_r +{ +#ifdef __cplusplus + private: +#endif //__cplusplus + union { - uint32_t value = static_cast<uint32_t>(memtype); - return value; - } - uint32_t get_memtype() const volatile + uint32_t CID3; // Byte 3 of Component ID (Lower 8 bits valid) + uint32_t word; + }; +#ifdef __cplusplus + public: + CONSTEXPR cid3_r() : CID3(static_cast<uint32_t>(0xB1)) {} + CONSTEXPR cid3_r(uint32_t init) : word(init) {} + CONSTEXPR void operator=(uint32_t value) { - uint32_t value = static_cast<uint32_t>(memtype); - return value; + word = value; } - CONSTEXPR axi_limit3_r &set_memtype(uint32_t value) + void operator=(uint32_t value) volatile { - memtype = ((1u << 4) - 1) & static_cast<uint32_t>(value); - return *this; + word = value; } - CONSTEXPR uint32_t get_max_outstanding_read_m1() const + CONSTEXPR operator uint32_t() { - uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); - return value; + return word; } - uint32_t get_max_outstanding_read_m1() const volatile + operator uint32_t() volatile { - uint32_t value = static_cast<uint32_t>(max_outstanding_read_m1); - return value; + return word; } - CONSTEXPR axi_limit3_r &set_max_outstanding_read_m1(uint32_t value) + cid3_r copy() volatile { - max_outstanding_read_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); return *this; } - CONSTEXPR uint32_t get_max_outstanding_write_m1() const + CONSTEXPR uint32_t get_CID3() const { - uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); + uint32_t value = static_cast<uint32_t>(CID3); return value; } - uint32_t get_max_outstanding_write_m1() const volatile + uint32_t get_CID3() const volatile { - uint32_t value = static_cast<uint32_t>(max_outstanding_write_m1); + uint32_t value = static_cast<uint32_t>(CID3); return value; } - CONSTEXPR axi_limit3_r &set_max_outstanding_write_m1(uint32_t value) + CONSTEXPR cid3_r &set_CID3(uint32_t value) { - max_outstanding_write_m1 = ((1u << 8) - 1) & static_cast<uint32_t>(value); + CID3 = static_cast<uint32_t>(value); return *this; } #endif //__cplusplus @@ -6354,9 +6354,10 @@ struct pmcr_r #ifdef __cplusplus public: CONSTEXPR pmcr_r() : - cnt_en(static_cast<uint32_t>(0)), event_cnt_rst(static_cast<uint32_t>(0)), - cycle_cnt_rst(static_cast<uint32_t>(0)), mask_en(static_cast<uint32_t>(0)), reserved0(static_cast<uint32_t>(0)), - num_event_cnt(static_cast<uint32_t>(4)), reserved1(static_cast<uint32_t>(0)) + cnt_en(static_cast<uint32_t>(0x0)), event_cnt_rst(static_cast<uint32_t>(0)), + cycle_cnt_rst(static_cast<uint32_t>(0)), mask_en(static_cast<uint32_t>(0x0)), + reserved0(static_cast<uint32_t>(0)), num_event_cnt(static_cast<uint32_t>(0x04)), + reserved1(static_cast<uint32_t>(0)) { } CONSTEXPR pmcr_r(uint32_t init) : word(init) {} @@ -7227,7 +7228,7 @@ struct pmccntr_lo_r }; #ifdef __cplusplus public: - CONSTEXPR pmccntr_lo_r() : CYCLE_CNT_LO(static_cast<uint32_t>(0)) {} + CONSTEXPR pmccntr_lo_r() : CYCLE_CNT_LO(static_cast<uint32_t>(0x00000000)) {} CONSTEXPR pmccntr_lo_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { @@ -7284,7 +7285,7 @@ struct pmccntr_hi_r }; #ifdef __cplusplus public: - CONSTEXPR pmccntr_hi_r() : CYCLE_CNT_HI(static_cast<uint32_t>(0)), reserved0(static_cast<uint32_t>(0)) {} + CONSTEXPR pmccntr_hi_r() : CYCLE_CNT_HI(static_cast<uint32_t>(0x0000)), reserved0(static_cast<uint32_t>(0)) {} CONSTEXPR pmccntr_hi_r(uint32_t init) : word(init) {} CONSTEXPR void operator=(uint32_t value) { @@ -7344,8 +7345,8 @@ struct pmccntr_cfg_r #ifdef __cplusplus public: CONSTEXPR pmccntr_cfg_r() : - CYCLE_CNT_CFG_START(static_cast<uint32_t>(0)), reserved0(static_cast<uint32_t>(0)), - CYCLE_CNT_CFG_STOP(static_cast<uint32_t>(0)), reserved1(static_cast<uint32_t>(0)) + CYCLE_CNT_CFG_START(static_cast<uint32_t>(0x00)), reserved0(static_cast<uint32_t>(0)), + CYCLE_CNT_CFG_STOP(static_cast<uint32_t>(0x00)), reserved1(static_cast<uint32_t>(0)) { } CONSTEXPR pmccntr_cfg_r(uint32_t init) : word(init) {} @@ -7786,7 +7787,7 @@ struct NPU_REG STRUCT dma_status1_r DMA_STATUS1; // 0x114 uint32_t unused4[10]; STRUCT clkforce_r CLKFORCE; // 0x140 - uint32_t DEBUG_ADDR; // 0x144 + uint32_t DEBUG_ADDRESS; // 0x144 uint32_t DEBUG_MISC; // 0x148 uint32_t DEBUGCORE; // 0x14c uint32_t unused5[12]; @@ -8059,7 +8060,7 @@ struct NPU_REG DMA_STATUS0 = 0; DMA_STATUS1 = 0; CLKFORCE = 0; - DEBUG_ADDR = 0; + DEBUG_ADDRESS = 0; DEBUG_MISC = 0; DEBUGCORE = 0; KERNEL_X = 0; diff --git a/src/ethosu_device.c b/src/ethosu_device.c index 273496d..7ce8fad 100644 --- a/src/ethosu_device.c +++ b/src/ethosu_device.c @@ -204,7 +204,7 @@ enum ethosu_error_codes ethosu_read_apb_reg(uint32_t start_address, uint16_t num #if !defined(ARM_NPU_STUB) uint32_t address = start_address; - ASSERT((start_address + num_reg) < NPU_IDS_REGISTERS_SIZE); + ASSERT((start_address + num_reg) < ID_REGISTERS_SIZE); for (int i = 0; i < num_reg; i++) { @@ -422,7 +422,7 @@ enum ethosu_error_codes ethosu_get_shram_data(int section, uint32_t *shram_p) #if !defined(ARM_NPU_STUB) int i = 0; uint32_t address = NPU_REG_SHARED_BUFFER0; - write_reg(NPU_REG_DEBUG_ADDR, section * BYTES_1KB); + write_reg(NPU_REG_DEBUG_ADDRESS, section * BYTES_1KB); while (address <= NPU_REG_SHARED_BUFFER255) { |