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| author | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2020-10-23 10:45:30 +0200 |
|---|---|---|
| committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2020-10-23 10:45:30 +0200 |
| commit | bad5a49832e921736747d3d9334fedf2b5571820 (patch) | |
| tree | b896a7d118468009477fbab60dc415083323b816 /src/ethosu_pmu.c | |
| parent | 4dc73dcea25d951971ae306481d1f201c8d6ebdd (diff) | |
| download | ethos-u-core-driver-bad5a49832e921736747d3d9334fedf2b5571820.tar.gz | |
Incorrect PMU cycle counter
The low and high PMU cycle counter registers were not combined
correctly.
Change-Id: I6b311b33527557f459fd87ebd5d4d3228625106a
Diffstat (limited to 'src/ethosu_pmu.c')
| -rw-r--r-- | src/ethosu_pmu.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/ethosu_pmu.c b/src/ethosu_pmu.c index f7cb957..57edacd 100644 --- a/src/ethosu_pmu.c +++ b/src/ethosu_pmu.c @@ -164,12 +164,12 @@ uint32_t ETHOSU_PMU_CNTR_Status(void) uint64_t ETHOSU_PMU_Get_CCNTR(void) { - uint32_t val_lo = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI); - uint32_t val_hi = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO); + uint32_t val_lo = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO); + uint32_t val_hi = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI); uint64_t val = ((uint64_t)val_hi << 32) | val_lo; uint64_t shadow = ((uint64_t)ethosu_drv.dev.pmccntr[1] << 32) | ethosu_drv.dev.pmccntr[0]; - LOG_DEBUG("%s: val=%llu, shadow=%llu\n", __FUNCTION__, val, shadow); + LOG_DEBUG("%s: val=%" PRIu64 ", shadow=%" PRIu64 "\n", __FUNCTION__, val, shadow); // Return the shadow variable in case the NPU was powered off and lost the cycle count if (shadow > val) |