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| author | Bhavik Patel <bhavik.patel@arm.com> | 2020-06-12 14:46:47 +0200 |
|---|---|---|
| committer | Bhavik Patel <bhavik.patel@arm.com> | 2020-06-26 14:12:04 +0200 |
| commit | e645fed716af167ae53e6f842e2baa85bdcb3c24 (patch) | |
| tree | 735a0cc11d8c667dfa9f6be5865355e6807e0d36 /src/ethosu_device.c | |
| parent | 2407e9646fe50709e36440d04d3f35367ea5bf81 (diff) | |
| download | ethos-u-core-driver-e645fed716af167ae53e6f842e2baa85bdcb3c24.tar.gz | |
MLBEDSW-2447 Set clock_q_enable & power_q_enable correctly
Bit [2] in CMD register is used to enable clock off using
clock q-interface and enable the master clock gate. Bit [3] is
used to enable power off using power q-interface.
The clock_q_enable bit is set when putting the Ethos-U into run
state.
The power_q_enable bit is set to 0 when running the command stream
and set to 1 after command stream has finished running.
Change-Id: Id9d1405376508e2af2ec0ddc2ebae8fb6c2f5cba
Diffstat (limited to 'src/ethosu_device.c')
| -rw-r--r-- | src/ethosu_device.c | 39 |
1 files changed, 33 insertions, 6 deletions
diff --git a/src/ethosu_device.c b/src/ethosu_device.c index 7df8b6f..cc8ca12 100644 --- a/src/ethosu_device.c +++ b/src/ethosu_device.c @@ -80,6 +80,8 @@ enum ethosu_error_codes ethosu_run_command_stream(const uint8_t *cmd_stream_ptr, const uint64_t *base_addr, int num_base_addr) { + enum ethosu_error_codes ret_code = ETHOSU_SUCCESS; + #if !defined(ARM_NPU_STUB) uint32_t qbase0; uint32_t qbase1; @@ -103,7 +105,8 @@ enum ethosu_error_codes ethosu_run_command_stream(const uint8_t *cmd_stream_ptr, write_reg(NPU_REG_QBASE0, qbase0); write_reg(NPU_REG_QBASE1, qbase1); write_reg(NPU_REG_QSIZE, qsize); - write_reg(NPU_REG_CMD, 1); + + ret_code = ethosu_set_command_run(); #else // NPU stubbed stream_length = cms_length; @@ -115,7 +118,7 @@ enum ethosu_error_codes ethosu_run_command_stream(const uint8_t *cmd_stream_ptr, #endif #endif - return ETHOSU_SUCCESS; + return ret_code; } enum ethosu_error_codes ethosu_is_irq_raised(uint8_t *irq_raised) @@ -140,13 +143,21 @@ enum ethosu_error_codes ethosu_is_irq_raised(uint8_t *irq_raised) enum ethosu_error_codes ethosu_clear_irq_status(void) { #if !defined(ARM_NPU_STUB) - write_reg(NPU_REG_CMD, 2); + struct cmd_r oldcmd; + oldcmd.word = read_reg(NPU_REG_CMD); + + struct cmd_r cmd; + cmd.word = 0; + cmd.clear_irq = 1; + cmd.clock_q_enable = oldcmd.clock_q_enable; + cmd.power_q_enable = oldcmd.power_q_enable; + write_reg(NPU_REG_CMD, cmd.word); #else #endif return ETHOSU_SUCCESS; } -// TODO Understand settings of privilege/sequrity level and update API. +// TODO Understand settings of privilege/security level and update API. enum ethosu_error_codes ethosu_soft_reset(void) { enum ethosu_error_codes return_code = ETHOSU_SUCCESS; @@ -400,7 +411,15 @@ enum ethosu_error_codes ethosu_get_irq_history_mask(uint16_t *irq_history_mask) enum ethosu_error_codes ethosu_clear_irq_history_mask(uint16_t irq_history_clear_mask) { #if !defined(ARM_NPU_STUB) - write_reg(NPU_REG_CMD, (uint32_t)irq_history_clear_mask << 16); + struct cmd_r oldcmd; + oldcmd.word = read_reg(NPU_REG_CMD); + + struct cmd_r cmd; + cmd.word = 0; + cmd.clock_q_enable = oldcmd.clock_q_enable; + cmd.power_q_enable = oldcmd.power_q_enable; + cmd.clear_irq_history = irq_history_clear_mask; + write_reg(NPU_REG_CMD, cmd.word); #else UNUSED(irq_history_clear_mask); #endif @@ -410,7 +429,15 @@ enum ethosu_error_codes ethosu_clear_irq_history_mask(uint16_t irq_history_clear enum ethosu_error_codes ethosu_set_command_run(void) { #if !defined(ARM_NPU_STUB) - write_reg(NPU_REG_CMD, 1); + struct cmd_r oldcmd; + oldcmd.word = read_reg(NPU_REG_CMD); + + struct cmd_r cmd; + cmd.word = 0; + cmd.transition_to_running_state = 1; + cmd.clock_q_enable = oldcmd.clock_q_enable; + cmd.power_q_enable = oldcmd.power_q_enable; + write_reg(NPU_REG_CMD, cmd.word); #else #endif return ETHOSU_SUCCESS; |