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| author | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2020-10-16 12:33:47 +0200 |
|---|---|---|
| committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2020-10-20 14:33:06 +0200 |
| commit | 4dc73dcea25d951971ae306481d1f201c8d6ebdd (patch) | |
| tree | 6c9d460f047e9123dda07480a6abb5efbcecb050 /src/ethosu_config.h | |
| parent | 5f8dad185b3e3a381fe2e3d16580a8a8e99f9db0 (diff) | |
| download | ethos-u-core-driver-4dc73dcea25d951971ae306481d1f201c8d6ebdd.tar.gz | |
PMU counter shadow
Storing PMU counters in shadow variables, in case the PMU was powered
off or soft reset.
Change-Id: I64ccf3fb6195f9be2d8315891ec612bb75404885
Diffstat (limited to 'src/ethosu_config.h')
| -rw-r--r-- | src/ethosu_config.h | 83 |
1 files changed, 0 insertions, 83 deletions
diff --git a/src/ethosu_config.h b/src/ethosu_config.h index 91fe660..7a9fae2 100644 --- a/src/ethosu_config.h +++ b/src/ethosu_config.h @@ -116,87 +116,4 @@ #define BASE_POINTER_OFFSET 0 #endif -#ifdef PMU_AUTOINIT -/* - * Register control - * b0 = CNT_EN = Enable counters (RW) - * b1 = EVENT_CNT_RST = Reset event counters (WO) - * b2 = CYCLE_CNT_RST = Reset cycle counter (WO) - * b[15:11] = Number of event counters (RO) - */ -#ifndef INIT_PMCR -#define INIT_PMCR 0x0 -#endif - -/* - * Bit k enables event counter k - * k=31 enables the cycle counter - * Read value is current status - */ -#ifndef INIT_PMCNTENSET -#define INIT_PMCNTENSET 0x0 -#endif - -/* - * Bit k disables event counter k - * k=31 disables the cycle counter - * Read value is current status - */ -#ifndef INIT_PMCNTENCLR -#define INIT_PMCNTENCLR 0x0 -#endif - -/* - * Overflow detection set - * Bit k is for counter k - * k=31 is cycle counter - */ -#ifndef INIT_PMOVSSET -#define INIT_PMOVSSET 0x0 -#endif - -/* - * Overflow detection clear - * Bit k is for counter k - * k=31 is cycle counter - */ -#ifndef INIT_PMOVSCLR -#define INIT_PMOVSCLR 0x0 -#endif - -/* - * Interrupt set - * Bit k is for counter k - * k=31 is cycle counter - */ -#ifndef INIT_PMINTSET -#define INIT_PMINTSET 0x0 -#endif - -/* - * Interrupt clear - * Bit k is for counter k - * k=31 is cycle counter - */ -#ifndef INIT_PMINTCLR -#define INIT_PMINTCLR 0x8003 -#endif - -/* Cycle counter - * 48 bits value - */ -#ifndef INIT_PMCCNTR -#define INIT_PMCCNTR 0x0 -#endif - -/* - * b[9:0] Start Event – this event number starts the cycle counter - * b[25:16] Stop Event – this event number stops the cycle counter - */ -#ifndef INIT_PMCCNTR_CFG -#define INIT_PMCCNTR_CFG 0x0 -#endif - -#endif /* #ifdef PMU_AUTOINIT */ - #endif /* #ifndef ETHOSU_CONFIG_H */ |