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| author | Bhavik Patel <bhavik.patel@arm.com> | 2020-06-18 15:25:15 +0200 |
|---|---|---|
| committer | Bhavik Patel <bhavik.patel@arm.com> | 2020-07-03 09:06:03 +0200 |
| commit | dae5be07b76e5361593d8c2fa4717970c2a5fc19 (patch) | |
| tree | bf051793cce3899f249522a8449c40432f11ef4b /include/pmu_ethosu.h | |
| parent | 8e32b0b72be3b109a921bcb33778eb515d27ef70 (diff) | |
| download | ethos-u-core-driver-dae5be07b76e5361593d8c2fa4717970c2a5fc19.tar.gz | |
MLBEDSW-2378 Set NPU base address in ethosu_init
Change-Id: I1145834000ff81d6e497a8fa77bf997478a80372
Diffstat (limited to 'include/pmu_ethosu.h')
| -rw-r--r-- | include/pmu_ethosu.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/include/pmu_ethosu.h b/include/pmu_ethosu.h index 64cd565..e83b879 100644 --- a/include/pmu_ethosu.h +++ b/include/pmu_ethosu.h @@ -19,6 +19,7 @@ #ifndef PMU_ETHOSU_H #define PMU_ETHOSU_H +#include "ethosu_device.h" #include <stdint.h> #ifdef __cplusplus @@ -122,6 +123,8 @@ uint32_t pmu_event_value(enum ethosu_pmu_event_type); /* Initialize the PMU driver */ void ethosu_pmu_driver_init(void); +void ethosu_pmu_driver_exit(void); + // CMSIS ref API /** \brief PMU Functions */ @@ -187,7 +190,7 @@ void ETHOSU_PMU_CNTR_Disable(uint32_t mask); - cycle counter activate (bit 31) \note ETHOSU specific. Usage breaks CMSIS complience */ -uint32_t ETHOSU_PMU_CNTR_Status(); +uint32_t ETHOSU_PMU_CNTR_Status(void); /** \brief Read cycle counter (64 bit) @@ -265,9 +268,9 @@ void ETHOSU_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); \note Sets overflow interrupt request bits for one or more of the following: - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) - cycle counter (bit 31) - \note ETHOSU specific. Usage breaks CMSIS complience + \note ETHOSU specific. Usage breaks CMSIS compliance */ -uint32_t ETHOSU_PMU_Get_IRQ_Enable(); +uint32_t ETHOSU_PMU_Get_IRQ_Enable(void); /** \brief Software increment event counter |