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author | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2022-05-12 11:35:33 +0200 |
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committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2022-05-13 12:49:05 +0200 |
commit | 1c0e7ae4bbf8ee81411b4c2e02c70ca892d17390 (patch) | |
tree | 49530e22edaff9916e31a22c3409fe6135b9b3be /ethosu_pmu/common.h | |
parent | 301399d9e0b619fb2e229c9a9223aaf31ec6bcfa (diff) | |
download | ethos-u-core-driver-22.05-rc3.tar.gz |
Base address 1 points at the TFLM arena and is by default routed
over AXI 0. For the spilling use case with both model and arena in
DRAM it would make more sense to route base addresses 0 and 1
over AXI 1.
For Ethos-U65 the default settings should correspond to the spilling
use case.
The AXI limits should have different max values depending on the NPU
architecture.
Change-Id: Icd317097e2cfdbfb39886e13c2cb2202651e5357
Diffstat (limited to 'ethosu_pmu/common.h')
0 files changed, 0 insertions, 0 deletions