// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "RedefineTestHelper.hpp" namespace armnnDelegate { void SqueezeSimpleTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 2, 2, 1 }; std::vector outputShape { 2, 2 }; std::vector squeezeDims { }; std::vector inputValues = { 1, 2, 3, 4 }; std::vector expectedOutputValues = { 1, 2, 3, 4 }; RedefineTest(tflite::BuiltinOperator_SQUEEZE, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, squeezeDims); } void SqueezeWithDimsTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 2, 2, 1 }; std::vector outputShape { 1, 2, 2 }; std::vector squeezeDims { -1 }; std::vector inputValues = { 1, 2, 3, 4 }; std::vector expectedOutputValues = { 1, 2, 3, 4 }; RedefineTest(tflite::BuiltinOperator_SQUEEZE, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, squeezeDims); } TEST_SUITE("Squeeze_GpuAccTests") { TEST_CASE ("Squeeze_Simple_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; SqueezeSimpleTest(backends); } TEST_CASE ("Squeeze_With_Dims_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; SqueezeWithDimsTest(backends); } } // TEST_SUITE("Squeeze_GpuAccTests") TEST_SUITE("Squeeze_CpuAccTests") { TEST_CASE ("Squeeze_Simple_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; SqueezeSimpleTest(backends); } TEST_CASE ("Squeeze_With_Dims_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; SqueezeWithDimsTest(backends); } } // TEST_SUITE("Squeeze_CpuAccTests") TEST_SUITE("Squeeze_CpuRefTests") { TEST_CASE ("Squeeze_Simple_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; SqueezeSimpleTest(backends); } TEST_CASE ("Squeeze_With_Dims_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; SqueezeWithDimsTest(backends); } } // TEST_SUITE("Squeeze_CpuRefTests") } // namespace armnnDelegate