From 303980c502c721f13d65e7087be6c0758df65044 Mon Sep 17 00:00:00 2001
From: Sadik Armagan <sadik.armagan@arm.com>
Date: Fri, 17 Apr 2020 12:45:14 +0100
Subject: IVGCVSW-4668 Add TENSOR_QUANT8_ASYMM_SIGNED data type support to
 CpuRef operators

Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Signed-off-by: Sadik Armagan <sadik.armagan@arm.com>
Change-Id: I094125ba80699cc3cf5226bda6662a54e6caa988
---
 src/backends/reference/workloads/RefTransposeWorkload.cpp | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/backends/reference/workloads/RefTransposeWorkload.cpp')

diff --git a/src/backends/reference/workloads/RefTransposeWorkload.cpp b/src/backends/reference/workloads/RefTransposeWorkload.cpp
index 242668b6b1..4e027bee2e 100644
--- a/src/backends/reference/workloads/RefTransposeWorkload.cpp
+++ b/src/backends/reference/workloads/RefTransposeWorkload.cpp
@@ -30,6 +30,7 @@ void RefTransposeWorkload<DataType>::Execute() const
 template class RefTransposeWorkload<DataType::BFloat16>;
 template class RefTransposeWorkload<DataType::Float16>;
 template class RefTransposeWorkload<DataType::Float32>;
+template class RefTransposeWorkload<DataType::QAsymmS8>;
 template class RefTransposeWorkload<DataType::QAsymmU8>;
 template class RefTransposeWorkload<DataType::QSymmS16>;
 
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