From 79a06a59bafadf736ca53c4240e87f9bbb657260 Mon Sep 17 00:00:00 2001
From: Teresa Charlin <teresa.charlinreyes@arm.com>
Date: Thu, 13 Jul 2023 17:16:45 +0100
Subject: IVGCVSW-7883 Front end and reference implementation for TILE

Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Signed-off-by: Cian McGriskin <cian.mcgriskin@arm.com>

Change-Id: I0afb2403fee11c5c1e58ea65e2525e99594d8f2d
---
 .../reference/workloads/RefTileWorkload.hpp        | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 src/backends/reference/workloads/RefTileWorkload.hpp

(limited to 'src/backends/reference/workloads/RefTileWorkload.hpp')

diff --git a/src/backends/reference/workloads/RefTileWorkload.hpp b/src/backends/reference/workloads/RefTileWorkload.hpp
new file mode 100644
index 0000000000..2fb8eab05e
--- /dev/null
+++ b/src/backends/reference/workloads/RefTileWorkload.hpp
@@ -0,0 +1,30 @@
+//
+// Copyright © 2023 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include "RefBaseWorkload.hpp"
+#include <armnn/backends/WorkloadData.hpp>
+
+#include "Tile.hpp"
+
+namespace armnn
+{
+
+    class RefTileWorkload : public RefBaseWorkload<TileQueueDescriptor>
+    {
+    public:
+        explicit RefTileWorkload(const TileQueueDescriptor& descriptor,
+                                 const WorkloadInfo& info);
+
+        void Execute() const override;
+        void ExecuteAsync(ExecutionData& executionData) override;
+
+    private:
+        void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
+
+    };
+
+} // namespace armnn
\ No newline at end of file
-- 
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