From b2d3ec5b1e938ef34facfdbcff83fc8e845d5f7c Mon Sep 17 00:00:00 2001
From: Teresa Charlin <teresa.charlinreyes@arm.com>
Date: Tue, 12 Apr 2022 22:07:09 +0100
Subject: IVGCVSW-6856 Add GATHERNd FrontEnd and Ref Implementation

* Add front end
* Add reference workload
* Add unit tests
* Add EndToEnd test

Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I4cebd17b18476df86162e2dda3366c10e80bd2f8
---
 .../reference/workloads/RefGatherNdWorkload.hpp    | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 src/backends/reference/workloads/RefGatherNdWorkload.hpp

(limited to 'src/backends/reference/workloads/RefGatherNdWorkload.hpp')

diff --git a/src/backends/reference/workloads/RefGatherNdWorkload.hpp b/src/backends/reference/workloads/RefGatherNdWorkload.hpp
new file mode 100644
index 0000000000..a0d91586cc
--- /dev/null
+++ b/src/backends/reference/workloads/RefGatherNdWorkload.hpp
@@ -0,0 +1,24 @@
+//
+// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include "RefBaseWorkload.hpp"
+
+namespace armnn
+{
+
+class RefGatherNdWorkload : public RefBaseWorkload<GatherNdQueueDescriptor>
+{
+public:
+    using RefBaseWorkload<GatherNdQueueDescriptor>::RefBaseWorkload;
+    void Execute() const override;
+    void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor)  override;
+private:
+    void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
+
+};
+
+} // namespace armnn
-- 
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