From b63a31170aee1d28267d83a4bc67b57708fb6b05 Mon Sep 17 00:00:00 2001
From: Matthew Sloyan <matthew.sloyan@arm.com>
Date: Wed, 8 Sep 2021 13:05:51 +0100
Subject: IVGCVSW-6163 Add Conv3d FrontEnd and Ref Implementation

 * Added front-end
 * Added Reference workload
 * Added Serializer & Deserializer support
 * Added unit tests
 * Added NDHWC DataLayout

Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com>
Change-Id: Iec4d39e7433b5334d52fa44cf8efc6bcd39319d8
---
 .../workloads/RefConvolution3dWorkload.hpp         | 38 ++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 src/backends/reference/workloads/RefConvolution3dWorkload.hpp

(limited to 'src/backends/reference/workloads/RefConvolution3dWorkload.hpp')

diff --git a/src/backends/reference/workloads/RefConvolution3dWorkload.hpp b/src/backends/reference/workloads/RefConvolution3dWorkload.hpp
new file mode 100644
index 0000000000..0373a8b900
--- /dev/null
+++ b/src/backends/reference/workloads/RefConvolution3dWorkload.hpp
@@ -0,0 +1,38 @@
+//
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include <backendsCommon/Workload.hpp>
+#include <backendsCommon/WorkloadData.hpp>
+#include "Decoders.hpp"
+#include "Encoders.hpp"
+
+namespace armnn
+{
+
+class RefConvolution3dWorkload : public BaseWorkload<Convolution3dQueueDescriptor>
+{
+public:
+    explicit RefConvolution3dWorkload(const Convolution3dQueueDescriptor& descriptor,
+                                      const WorkloadInfo& info);
+
+
+    void Execute() const override;
+    void ExecuteAsync(WorkingMemDescriptor& workingMemDescriptor)  override;
+
+private:
+    void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const;
+    std::unique_ptr<ScopedTensorHandle> m_Weight;
+    std::unique_ptr<ScopedTensorHandle> m_Bias;
+
+    std::unique_ptr<Decoder<float>> m_FilterDecoder;
+    std::unique_ptr<Decoder<float>> m_BiasDecoder;
+
+    TensorShape m_FilterShape;
+};
+
+} //namespace armnn
+
-- 
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